ST92185B STMicroelectronics, ST92185B Datasheet - Page 140

• Manufacturer Part Number: ST92185B
• Description: 16k/24k/32k Rom Hcmos Mcu With On-screen-display
• Manufacturer: STMicroelectronics

ST92185B - SYNC CONTROLLER
SYNC CONTROLLER (Cont’d)
7.5.5 Register Description
SYNC CONTROLLER CONTROL AND STATUS
REGISTER 0 (SCCS0R)
R242 - Read/Write
Register Page: 35
Reset value: 0000 0000 (00h)
Bit 7= VPOL. VSYNC Polarity
When MOD[1:0] are reset, this bit configures the
polarity of the VSYNC input.
0: Negative polarity (leading edge is falling edge)
1: Positive polarity (leading edge is rising edge)
For other cases:
Bit 6= HPOL. HSYNC/CSYNC Polarity .
0: Negative polarity (leading edge is falling edge)
1: Positive polarity (leading edge is rising edge)
Bit 5= VSEP. Separate Sync
When MOD[1:0] are reset:
0: The standard mode using two inputs (VSYNC
1: The Composite Sync mode is activated; the
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VPOL
MOD1
and HSYNC) is activated.
HSYNC/CSYNC input will be used to get both H
and V signals.
0
x
x
1
1
HPOL
MOD0 VPOL
0
1
1
x
x
VSEP
x
0
1
0
1
VDLY
VSYNC polarity control
interlaced
non-interlaced
interlaced
non-interlaced
HSF3 HSF2
HSF1 HSF0
0
For other cases:
Bit 4= VDLY. Vertical Delay control bit .
This bit is active only if the Composite Sync mode
is enabled. The selection of this bit can effect
noise margin (longer delay is better) and the field
detection.
0: Vertical is generated after detecting a pulse
1: Vertical is generated after detecting a pulse
Bit 3:0= HSF. Horizontal Shift for Field detection .
These 4 bits program the delay, in steps of 4µs,
applied to the HSYNC pulse in order to properly
determine the field information by comparison with
VSYNC. This value is a chassis constant depend-
ing upon the way the separate H/V signals are
generated.
MOD1
greater than 16µs
greater than 32µs
0
x
x
1
1
MOD0
0
1
1
x
x
VSEP
x
0
1
0
1
CSO alternate function
disabled
disabled
disabled
enabled
enabled