DSPIC33FJ12MC202 Microchip Technology Inc., DSPIC33FJ12MC202 Datasheet - Page 60

• Manufacturer Part Number: DSPIC33FJ12MC202
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

dsPIC33FJ12MC201/202
5.1
If clock switching is enabled, the system clock source at
device Reset is chosen as shown in Table 5-2. If clock
switching is disabled, the system clock source is always
selected according to the oscillator Configuration bits.
Refer to Section 7.0 “Oscillator Configuration” for
further details.
TABLE 5-2:
TABLE 5-3:
DS70265B-page 58
POR
BOR
MCLR
WDT
Software
Illegal Opcode
Uninitialized W
Trap Conflict
Note 1:
Reset Type
Reset Type
WDTR
MCLR
SWR
POR
BOR
2:
3:
4:
5:
6:
Clock Source Selection at Reset
T
T
Power-up Timer delay (if regulator is disabled). T
states, including waking from Sleep mode, only if the regulator is enabled.
T
T
oscillator clock to the system.
T
T
STARTUP
OST
POR
RST
LOCK
FSCM
= Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing the
= Internal state Reset time (20 μs nominal).
= Power-on Reset delay (10 μs nominal).
Oscillator Configuration bits
(FNOSC<2:0>)
COSC Control bits
(OSCCON<14:12>)
OSCILLATOR SELECTION vs.
TYPE OF RESET (CLOCK
SWITCHING ENABLED)
RESET DELAY TIMES FOR VARIOUS DEVICE RESETS
= PLL lock time (20 μs nominal).
= Fail-Safe Clock Monitor delay (100 μs nominal).
Any Clock
Any Clock
Any Clock
EC, FRC, LPRC
ECPLL, FRCPLL
XT, HS, SOSC
XTPLL, HSPLL
EC, FRC, LPRC
ECPLL, FRCPLL
XT, HS, SOSC
XTPLL, HSPLL
Any Clock
Any Clock
Any Clock
Clock Source Determinant
= Conditional POR delay of 20 μs nominal (if on-chip regulator is enabled) or 64 ms nominal
Clock Source
T
T
T
T
POR
POR
POR
POR
T
T
T
T
SYSRST Delay
STARTUP
STARTUP
STARTUP
STARTUP
+ T
+ T
+ T
+ T
Preliminary
STARTUP
STARTUP
STARTUP
STARTUP
T
T
T
T
T
T
RST
RST
RST
RST
RST
RST
+ T
+ T
+ T
+ T
STARTUP
RST
RST
RST
RST
+ T
+ T
+ T
+ T
5.2
The Reset times for various types of device Reset are
summarized in Table 5-3. The system Reset signal,
SYSRST, is released after the POR and PWRT delay
times expire.
The time at which the device actually begins to execute
code also depends on the system oscillator delays,
which include the Oscillator Start-up Timer (OST) and
the Phase-Locked Loop (PLL) lock time. The OST and
PLL lock times occur in parallel with the applicable
SYSRST delay times.
The FSCM delay determines the time at which the
FSCM begins to monitor the system clock source after
the SYSRST signal is released.
RST
RST
RST
RST
is also applied to all returns from powered-down
Device Reset Times
System Clock
T
T
OST
OST
T
T
Delay
T
T
LOCK
LOCK
+ T
+ T
—
OST
—
OST
—
—
—
—
—
—
LOCK
LOCK
© 2007 Microchip Technology Inc.
FSCM
T
T
T
T
T
T
Delay
FSCM
FSCM
FSCM
FSCM
FSCM
FSCM
—
—
—
—
—
—
—
—
1, 2, 3
1, 2, 3, 5, 6
1, 2, 3, 4, 6
1, 2, 3, 4, 5, 6
3
3, 5, 6
3, 4, 6
3, 4, 5, 6
3
3
3
3
3
3
Notes