DSPIC33FJ12MC202 Microchip Technology Inc., DSPIC33FJ12MC202 Datasheet - Page 139

• Manufacturer Part Number: DSPIC33FJ12MC202
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

12.0
The input capture module is useful in applications
requiring frequency (period) and pulse measurement.
The dsPIC33FJ12MC201/202 devices support up to
eight input capture channels.
The input capture module captures the 16-bit value of
the selected Time Base register when an event occurs
at the ICx pin. The events that cause a capture event
are listed below in three categories:
1.
2.
FIGURE 12-1:
© 2007 Microchip Technology Inc.
Note:
- Capture timer value on every falling edge of
- Capture timer value on every rising edge of
Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.
Simple Capture Event modes:
input at ICx pin
input at ICx pin
Capture timer value on every edge (rising and
falling)
ICx Pin
INPUT CAPTURE
This data sheet summarizes the features
of the dsPIC33FJ12MC201/202 devices.
It is not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to the
“dsPIC33F Family Reference Manual”.
Please see the Microchip web site
(www.microchip.com)
dsPIC33F
chapters.
Prescaler
(1, 4, 16)
Counter
3
INPUT CAPTURE BLOCK DIAGRAM
System Bus
Family
ICxCON
ICM<2:0> (ICxCON<2:0>)
ICOV, ICBNE (ICxCON<4:3>)
Mode Select
Reference
for
Edge Detection Logic
Clock Synchronizer
the
ICxI<1:0>
and
Manual
latest
Preliminary
dsPIC33FJ12MC201/202
(in IFSn Register)
Set Flag ICxIF
Interrupt
Logic
3.
Each input capture channel can select one of two
16-bit timers (Timer2 or Timer3) for the time base.
The selected timer can use either an internal or
external clock.
Other operational features include:
• Device wake-up from capture pin during CPU
• Interrupt on input capture event
• 4-word FIFO buffer for capture values
• Use of input capture to provide additional sources
- Capture timer value on every 4th rising edge
- Capture timer value on every 16th rising
Sleep and Idle modes
- Interrupt optionally generated after 1, 2, 3 or
of external interrupts
Prescaler Capture Event modes:
of input at ICx pin
edge of input at ICx pin
4 buffer locations are filled
Logic
FIFO
R/W
From 16-bit Timers
TMR2 TMR3
1
ICxBUF
16
0
DS70265B-page 137
16
ICTMR
(ICxCON<7>)