DSPIC33FJ12MC202 Microchip Technology Inc., DSPIC33FJ12MC202 Datasheet - Page 153

• Manufacturer Part Number: DSPIC33FJ12MC202
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

14.10 Independent PWM Output
Independent PWM Output mode is required for driving
certain types of loads. A particular PWM output pair is
in
corresponding PMODx bit in the PWMxCON1 register
is set. No dead-time control is implemented between
adjacent PWM I/O pins when the module is operating
in the Independent PWM Output mode and both I/O
pins are allowed to be active simultaneously.
In the Independent PWM Output mode, each duty
cycle generator is connected to both of the PWM I/O
pins in an output pair. By using the associated Duty
Cycle register and the appropriate bits in the
PxOVDCON register, the programmer can select the
following signal output options for each PWM I/O pin
operating in this mode:
• I/O pin outputs PWM signal
• I/O pin inactive
• I/O pin active
14.11 Single Pulse PWM Operation
The PWM module produces single pulse outputs when
the PxTCON control bits PTMOD<1:0> = 10. Only
edge-aligned outputs can be produced in the Single
Pulse mode. In Single Pulse mode, the PWM I/O pin(s)
are driven to the active state when the PTEN bit is set.
When a match with a Duty Cycle register occurs, the
PWM I/O pin is driven to the inactive state. When a
match with the PxTPER register occurs, the PxTMR
register is cleared, all active PWM I/O pins are driven
to the inactive state, the PTEN bit is cleared and an
interrupt is generated.
14.12 PWM Output Override
The PWM output override bits allow the user
application to manually drive the PWM I/O pins to
specified logic states, independent of the duty cycle
comparison units.
All control bits associated with the PWM output over-
ride function are contained in the PxOVDCON register.
The upper half of the PxOVDCON register contains
eight bits, POVDxH<4:1> and POVDxL<4:1>, that
determine which PWM I/O pins will be overridden. The
lower half of the PxOVDCON register contains eight
bits, POUTxH<4:1> and POUTxL<4:1>, that determine
the state of the PWM I/O pins when a particular output
is overridden via the POVD bits.
14.12.1
When a PWMxL pin is driven active via the
PxOVDCON register, the output signal is forced to be
the complement of the corresponding PWMxH pin in
the pair. Dead-time insertion is still performed when
PWM channels are overridden manually.
© 2007 Microchip Technology Inc.
the
Independent
COMPLEMENTARY OUTPUT MODE
Output
mode
when
Preliminary
the
dsPIC33FJ12MC201/202
14.12.2
If the OSYNC bit in the PWMxCON2 register is set, all
output overrides performed via the PxOVDCON
register are synchronized to the PWM time base.
Synchronous output overrides occur at the following
times:
• Edge-Aligned mode – When PxTMR is zero
• Center-Aligned modes – When PxTMR is zero
14.13 PWM Output and Polarity Control
Three device Configuration bits are associated with the
PWM module that provide PWM output pin control:
• HPOL Configuration bit
• LPOL Configuration bit
• PWMPIN Configuration bit
These three bits in the FPOR Configuration register
(see Section 20.0 “Special Features”) work in
conjunction
(PENxH<4:1>,
PWMxCON1 SFR. The Configuration bits and PWM
Enable bits ensure that the PWM pins are in the
correct states after a device Reset occurs.
The PWMPIN configuration fuse allows the PWM
module outputs to be optionally enabled on a device
Reset. If PWMPIN = 0, the PWM outputs are driven to
their inactive states at Reset. If PWMPIN = 1 (default),
the PWM outputs will be tri-stated. The HPOL bit
specifies the polarity for the PWMxH outputs. The
LPOL bit specifies the polarity for the PWMxL outputs.
14.13.1
The PENxH<4:1> and PENxL<4:1> control bits in the
PWMxCON1 SFR enable each high PWM output pin
and each low PWM output pin, respectively. If a
particular PWM output pin is not enabled, it is treated
as a general purpose I/O pin.
14.14 PWM Fault Pins
There is one Fault pin (FLTAx) associated with the
PWM module. When asserted, this pin can optionally
drive each of the PWM I/O pins to a defined state.
and the value of PxTMR matches PxTPER
OVERRIDE SYNCHRONIZATION
OUTPUT PIN CONTROL
with
PENxL<4:1>)
the
eight
PWM
located
DS70265B-page 151
Enable
in
bits
the