DSPIC33FJ12MC202 Microchip Technology Inc., DSPIC33FJ12MC202 Datasheet - Page 18

• Manufacturer Part Number: DSPIC33FJ12MC202
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

dsPIC33FJ12MC201/202
REGISTER 2-2:
DS70265B-page 16
bit 15
bit 7
Legend:
R = Readable bit
0’ = Bit is cleared
bit 15-13
bit 12
bit 11
bit 10-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
Note 1:
R/W-0
SATA
U-0
—
2:
This bit will always read as ‘0’.
The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.
Unimplemented: Read as ‘0’
US: DSP Multiply Unsigned/Signed Control bit
1 = DSP engine multiplies are unsigned
0 = DSP engine multiplies are signed
EDT: Early DO Loop Termination Control bit
1 = Terminate executing DO loop at end of current loop iteration
0 = No effect
DL<2:0>: DO Loop Nesting Level Status bits
111 = 7 DO loops active
•
•
•
001 = 1 DO loop active
000 = 0 DO loops active
SATA: ACCA Saturation Enable bit
1 = Accumulator A saturation enabled
0 = Accumulator A saturation disabled
SATB: ACCB Saturation Enable bit
1 = Accumulator B saturation enabled
0 = Accumulator B saturation disabled
SATDW: Data Space Write from DSP Engine Saturation Enable bit
1 = Data space write saturation enabled
0 = Data space write saturation disabled
ACCSAT: Accumulator Saturation Mode Select bit
1 = 9.31 saturation (super saturation)
0 = 1.31 saturation (normal saturation)
IPL3: CPU Interrupt Priority Level Status bit 3
1 = CPU interrupt priority level is greater than 7
0 = CPU interrupt priority level is 7 or less
PSV: Program Space Visibility in Data Space Enable bit
1 = Program space visible in data space
0 = Program space not visible in data space
R/W-0
SATB
U-0
—
CORCON: CORE CONTROL REGISTER
C = Clear only bit
W = Writable bit
‘x = Bit is unknown
SATDW
R/W-1
U-0
—
ACCSAT
R/W-0
R/W-0
US
Preliminary
-n = Value at POR
(1)
U = Unimplemented bit, read as ‘0’
(2)
EDT
IPL3
R/W-0
R/C-0
(1)
(2)
R/W-0
PSV
R-0
© 2007 Microchip Technology Inc.
‘1’ = Bit is set
DL<2:0>
R/W-0
RND
R-0
R/W-0
R-0
IF
bit 8
bit 0