DSPIC33FJ12MC202 Microchip Technology Inc., DSPIC33FJ12MC202 Datasheet - Page 148

• Manufacturer Part Number: DSPIC33FJ12MC202
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

dsPIC33FJ12MC201/202
14.3
The PWM time base is provided by a 15-bit timer with
a prescaler and postscaler. The time base is accessible
via the P
bit, PTDIR, that indicates the present count direction of
the PWM time base.
• If PTDIR is cleared, P
• If PTDIR is set, PxTMR is counting downward.
The PWM time base is configured using the PxTCON
SFR. The time base is enabled or disabled by setting
or clearing the PTEN bit in the P
is not cleared when the PTEN bit is cleared in software.
The P
P
to P
matches the value in P
will either reset to ‘0’ or reverse the count direction on
the next occurring clock cycle. The action taken
depends on the operating mode of the time base.
The PWM time base can be configured for four different
modes of operation:
• Free-Running mode
• Single-Shot mode
• Continuous Up/Down Count mode
• Continuous Up/Down Count mode with interrupts
These four modes are selected by the PTMOD<1:0>
bits in the P
support center-aligned PWM generation. The Single-
Shot mode allows the PWM module to support pulse
control of certain Electronically Commutative Motors
(ECMs).
The interrupt signals generated by the PWM time base
depend on the mode selection bits (PTMOD<1:0>) and
the postscaler bits (PTOPS<3:0>) in the P
DS70265B-page 146
X
Note:
for double updates
TMR. The user application must write a 15-bit value
X
TPER<14:0>. When the value in P
X
TPER SFR sets the counting period for
X
PWM Time Base
TMR SFR. P
If the PWM Period register is set to
0x0000, the timer will stop counting and
the interrupt and Special Event Trigger will
not be generated, even if the special event
value is also 0x0000. The module will not
update the PWM Period register if it is
already at 0x0000; therefore, the user
application must disable the module in to
update the PWM Period register.
X
TCON SFR. The Up/Down Count modes
X
TMR<15> is a read-only status
X
X
TMR is counting upward.
TPER<14:0>, the time base
X
TCON SFR. P
X
X
TCON SFR.
TMR<14:0>
X
TMR
Preliminary
14.3.1
In Free-Running mode, the PWM time base counts
upwards until the value in the PWM Time Base Period
register (P
reset on the following input clock edge, and the time
base will continue to count upward as long as the PTEN
bit remains set.
When the PWM time base is in the Free-Running mode
(PTMOD<1:0> = 00), an interrupt event is generated
each time a match with the P
and the P
selection bits can be used in this mode of the timer to
reduce the frequency of interrupt events.
14.3.2
In Single-Shot mode, the PWM time base begins
counting upward when the PTEN bit is set. When the
value in the P
ister, the P
input clock edge, and the PTEN bit will be cleared by
the hardware to halt the time base.
When the PWM time base is in Single-Shot mode
(PTMOD<1:0> = 01), an interrupt event is generated
when a match with the P
PxTMR register is reset to zero on the following input
clock edge and the PTEN bit is cleared. The postscaler
selection bits have no effect in this mode of the timer.
14.3.3
In Continuous Up/Down Count modes, the PWM time
base counts upward until the value in the P
register is matched. The timer will begin counting
downwards on the following input clock edge. The
PTDIR bit in the P
indicates the counting direction. The PTDIR bit is set
when the timer counts downward.
In the Up/Down Count mode (PTMOD<1:0> = 10), an
interrupt event is generated each time the value of the
P
begins to count upward. The postscaler selection bits
can be used in this mode of the timer to reduce the
frequency of interrupt events.
X
TMR register becomes zero and the PWM time base
X
X
TMR register is reset to zero. The postscaler
X
TPER) is matched. The P
FREE-RUNNING MODE
SINGLE-SHOT MODE
CONTINUOUS UP/DOWN COUNT
MODES
TMR register will be reset on the following
X
TMR register matches the P
X
TMR SFR is read-only and
© 2007 Microchip Technology Inc.
X
TPER register occurs. The
X
TPER register occurs
X
TMR register is
X
TPER reg-
X
TPER