DSPIC33FJ12MC202 Microchip Technology Inc., DSPIC33FJ12MC202 Datasheet - Page 218

• Manufacturer Part Number: DSPIC33FJ12MC202
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

dsPIC33FJ12MC201/202
20.5
dsPIC33FJ12MC201/202 devices implement a JTAG
interface, which supports boundary scan device test-
ing, as well as in-circuit programming. Detailed infor-
mation on this interface will be provided in future
revisions of the document.
20.6
The dsPIC33FJ12MC201/202 devices can be serially
programmed while in the end application circuit. This is
done with two lines for clock and data and three other
lines for power, ground and the programming
sequence. Serial programming allows customers to
manufacture boards with unprogrammed devices and
then program the digital signal controller just before
shipping the product. Serial programming also allows
the most recent firmware or a custom firmware to be
programmed. Refer to the “dsPIC33F/PIC24H Flash
Programming Specification” (DS70152) document for
details about In-Circuit Serial Programming (ICSP).
Any of the three pairs of programming clock/data pins
can be used:
• PGC1/EMUC1 and PGD1/EMUD1
• PGC2/EMUC2 and PGD2/EMUD2
• PGC3/EMUC3 and PGD3/EMUD3
20.7
When MPLAB
circuit debugging functionality is enabled. This function
allows simple debugging functions when used with
MPLAB IDE. Debugging functionality is controlled
through the EMUCx (Emulation/Debug Clock) and
EMUDx (Emulation/Debug Data) pin functions.
Any of the three pairs of debugging clock/data pins can
be used:
• PGC1/EMUC1 and PGD1/EMUD1
• PGC2/EMUC2 and PGD2/EMUD2
• PGC3/EMUC3 and PGD3/EMUD3
To use the in-circuit debugger function of the device,
the design must implement ICSP connections to
MCLR, V
pin pair. In addition, when the feature is enabled, some
of the resources are not available for general use.
These resources include the first 80 bytes of data RAM
and two I/O pins.
DS70265B-page 216
JTAG Interface
In-Circuit Debugger
DD
In-Circuit Serial Programming
, V
®
SS
ICD 2 is selected as a debugger, the in-
, PGC, PGD and the EMUDx/EMUCx
Preliminary
20.8
The
intermediate implementation of CodeGuard Security.
CodeGuard Security enables multiple parties to
securely share resources (memory, interrupts and
peripherals) on a single chip. This feature helps protect
individual Intellectual Property in collaborative system
designs.
When coupled with software encryption libraries,
CodeGuard Security can be used to securely update
Flash even when multiple IPs reside on the single chip.
The code protection features vary depending on the
actual dsPIC33F implemented. The following sections
provide an overview of these features.
Secure segment and RAM protection is not
implemented in dsPIC33FJ12MC201/202 devices.
TABLE 20-3:
BSS<2:0> = x11
BSS<2:0> = x10
BSS<2:0> = x01
BSS<2:0> = x00
Note:
CONFIG BITS
dsPIC33FJ12MC201/202
1792
256
768
0K
Code Protection and
CodeGuard™ Security
Refer to Section 23.
Security” (DS70199) of the dsPIC33F
Family Reference Manual for further
information on usage, configuration and
operation of CodeGuard Security.
CODE FLASH SECURITY
SEGMENT SIZES FOR
12 KBYTE DEVICES
© 2007 Microchip Technology Inc.
GS = 3840 IW
GS = 3584 IW
GS = 3072 IW
BS = 1792 IW
GS = 2048 IW
VS = 256 IW
VS = 256 IW
BS = 256 IW
VS = 256 IW
BS = 768 IW
VS = 256 IW
devices
“CodeGuard™
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0001FEh
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0003FEh
000400h
0007FEh
000800h
000FFEh
001000h
001FFEh
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000200h
0003FEh
000400h
0007FEh
000800h
000FFEh
001000h
001FFEh
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0007FEh
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offer
the