FIN1216 Fairchild Semiconductor, FIN1216 Datasheet
FIN1216
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FIN1216 Summary of contents
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... LVDS link. Every cycle of transmit clock 21 bits of input LVTTL data are sampled and trans- mitted. The FIN1218 and FIN1216 receive and convert the 3 serial LVDS data streams back into 21 bits of LVTTL data. Refer to Table 1 for a matrix summary of the Serializers and De- serializers available ...
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... TABLE 1. Serializers/De-Serializers Chip Matrix Part CLK Frequency FIN1217 85 FIN1218 85 FIN1215 66 FIN1216 66 Block Diagrams Transmitter Functional Diagram for FIN1217 and FIN1215 Receiver Functional Diagram for FIN1218 and FIN1216 www.fairchildsemi.com LVTTL IN LVDS OUT LVDS IN LVTTL OUT Package 48 TSSOP 21 48 TSSOP ...
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Transmitters Pin Descriptions Pin Names I/O Type Number of Pins TxIn I 21 TxCLKIn TxOut O TxOut O TxCLKOut O TxCLKOut O PwrDn I 1 PLL PLL GND I LVDS V ...
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... Power Supply Pin for LVDS Inputs CC LVDS GND I 3 Ground Pins for LVDS Inputs Power Supply for LVTTL Outputs CC GND I 5 Ground Pins for LVTTL Outputs NC No Connect Connection Diagram FIN1218 and FIN1216 (3:21 Receiver) www.fairchildsemi.com Description of Signals Pin Assignment for TSSOP 4 ...
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Truth Tables Transmitter Truth Table Inputs TxIn TxCLKIn Active Active Active L/H/Z F Active HIGH Logic Level L LOW Logic Level X Don’t Care Z High Impedance F Floating Note 2: The outputs of the ...
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Absolute Maximum Ratings Power Supply Voltage ( TTL/CMOS Input/Output Voltage LVDS Input/Output Voltage LVDS Output Short Circuit Current (I ) OSD Storage Temperature Range (T ) STG Maximum Junction Temperature ( Lead Temperature ( ...
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Transmitter AC Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified. Symbol Parameter t Transmit Clock Period TCP t Transmit Clock (TxCLKIn) HIGH Time TCH t Transmit Clock Low Time TCL t TxCLKIn Transition Time (Rising and ...
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Receiver DC Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified. (Note 16) Symbol Parameter LVTTL/CMOS DC Characteristics V Input High Voltage IH V Input Low Voltage IL V Output High Voltage OH V Output Low Voltage ...
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Receiver AC Electrical Characteristics Over supply voltage and operating temperatures, unless otherwise specified Symbol Parameter t RxCLKOut LOW Time RCOL t RxCLKOut HIGH Time RCOH t RxOut Valid Prior to RxCLKOut RSRC t RxOut Valid After RxCLKOut RHRC t Receiver ...
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FIGURE 1. Differential LVDS Output DC Test Circuit Note A: For all input pulses ns Note B: C includes all probe and jig capacitance. L FIGURE 2. Differential Receiver Voltage Definitions and Propagation ...
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AC Loading and Waveforms Note: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVTTL/CMOS I/O. Depending on the valid strobe edge of transmitter, the TxCLKIn can be either rising or falling edge data ...
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AC Loading and Waveforms FIGURE 8. Receiver Setup/Hold and HIGH/LOW Times FIGURE 9. Transmitter Clock In to Clock Out Delay (Rising Edge Strobe) FIGURE 10. Receiver Clock In to Clock Out Delay (Falling Edge Strobe) www.fairchildsemi.com (Continued) 12 ...
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AC Loading and Waveforms FIGURE 11. Transmitter Phase Lock Loop Set Time FIGURE 12. Receiver Phase Lock Loop Set Time FIGURE 13. Transmitter Power-Down Delay (Continued) 13 www.fairchildsemi.com ...
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AC Loading and Waveforms FIGURE 14. Receiver Power-Down Delay Note: This output data pulse position works for both transmitter with 21 TTL inputs except the LVDS output bit mapping difference. All the information in this diagram tells that the skew ...
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AC Loading and Waveforms FIGURE 17. Receiver Input Strobe Bit Position Note the budget for the cable skew and source clock skew plus ISI (Inter-Symbol Interference). RSKM Note: The minimum and maximum pulse position values are based on ...
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AC Loading and Waveforms Note: This jitter pattern is used to test the jitter response (Clock Out) of the device over the power supply range with worst jitter input. The specific test methodology is as follows: • Switching input data ...
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Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...