PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 65

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PM5381-BI

Manufacturer Part Number
PM5381-BI
Description
ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
Manufacturer
PMC-Sierra, Inc.
Datasheet

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Document ID: PMC-2000489, Issue 4
APS Serial Data Interface (20)
Pin Name
TERR
TMOD[1:0]
Pin Name
APSIFPCLK
Type
Input
Input
Type
Input
Pin
No.
A17
B17
A18
Pin
No.
P3
Function
The POS-PHY transmit error (TERR) signal is used to
indicate that the current packet must be aborted. Packets
marked with TERR will have the abort sequence appended
when transmitted. TERR should only be asserted during the
last word of the packet being transferred on TDAT[31:0].
TERR is only considered valid when TENB and TEOP are
simultaneously asserted.
TERR is only used for POS-PHY operation and is sampled on
the rising edge of TFCLK.
The POS-PHY transmit word modulo (TMOD[1:0]) bus
indicates the size of the current word when configured for
packet mode. During a packet transfer, every word on
TDAT[31:0] must contain four valid bytes of packet data
except at the end of the packet where the word is composed
of 1, 2, 3, or 4 valid bytes. The number of valid bytes in this
last word is specified by TMOD[1:0]
TMOD[1:0] is considered valid only when TENB is
simultaneously asserted. TMOD[1:0] is only used for POS-
PHY operation and is sampled on the rising edge of TFCLK.
Function
The APS input frame pulse clock (APSIFPCLK) provides a
jitter-free reference clock used to sample the APS input frame
pulse (APSIFP). The 777.76 MHz Clock Synthesis Unit of the
APS Port also uses this clock as its reference.
APSIFPCLK is expected to cycle at a 77.76 MHz rate, and
must be synchronous with respect to REFCLK_P /
REFCLK_N to ensure that APSIFPCLK is an exact divide-by-
two in frequency, compared to REFCLK_P / REFCLK_N.
TMOD[1:0] = “00”
TMOD[1:0] = “01”
TMOD[1:0] = “10”
TMOD[1:0] = “11”
S/UNI-2488 Telecom Standard Product Datasheet
TDAT[31:0] valid
TDAT[31:8] valid
TDAT[31:16] valid
TDAT[31:24] valid
Released
65

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