PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 361

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
IDLEPASS
DELINDIS
STRIP_SEL
INVERT
The IDLEPASS bit controls the function of the ATM Idle Cell filter. It is only valid when in
ATM mode. When IDLEPASS is written with logic 0, all cells that match the Idle Cell
Header Pattern and Idle Cell Header Mask are filtered out. When IDLEPASS is enabled, the
Idle Cell Header Pattern and Mask register bits are ignored. The default state of this bit and
the bits in the RCFP Idle Cell Header and Mask Register enable the dropping of Idle cells.
When DELINDIS is set to logic 1, all payload data read by the RCFP is passed to the FIFO
interface without the requirement of having to find cell delineation or packet delineation first.
In ATM mode the DELINDIS bit is used to disable all ATM cell filtering and ATM cell
delineation. If cell alignment has been reached before DELINDIS is enabled, then the current
cell alignment position is kept.
In POS mode the DELINDIS bit is used to disable the HDLC flag alignment, byte destuffing
and flag removal. The data stream is arbitrarily segmented into 64 byte long packets. FCS
and descrambling operations still follow how they have been set in their respective
configuration registers.
When DELINDIS mode is used, the RBY_MODE bit in register 0743H must be set for
proper counter operation. If this is not done, the counters will be incorrect.
The frame check sequence stripping bit (STRIP_SEL) selects the CRC stripping mode of the
RCFP. When STRIP_SEL is logic 1, CRC stripping is enabled. When STRIP_SEL is logic
0, CRC stripping is disabled. Note that CRC_SEL[1:0] must not equal "00", (no CRC) for
stripping to be enabled. When stripping is enabled, the received packet FCS or ATM cell
HCS byte(s) are not passed to the RXSDQ FIFO. When STRIP is disabled, the received
packet FCS are transferred over the FIFO interface. When DELINDIS is enabled, packets
and cells are not delineated therefore the value of STRIP_SEL is ignored. The STRIP_SEL
bit must be set to logic 1 if working in ATM mode.
The data inversion bit (INVERT) configures the processor to logically invert the incoming
stream before processing it. When INVERT is set to logic 1, the stream is logically inverted
before processing. When INVERT is set to logic 0, the stream is not inverted before
processing.
S/UNI-2488 Telecom Standard Product Datasheet
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361