PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 282
PM5381-BI
Manufacturer Part Number
PM5381-BI
Description
ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
Manufacturer
PMC-Sierra, Inc.
Datasheet
1.PM5381-BI.pdf
(586 pages)
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Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
PBIPEE
PREIEE
The path BIP-8 error interrupt enable (PBIPEE) bit controls the activation of the interrupt
(INTB) output. When PBIPEE is set to logic 1, the PBIPEI pending interrupt will assert the
interrupt (INTB) output. When PBIPEE is set to logic 0, the PBIPEI pending interrupt will
not assert the interrupt (INTB) output.
The path REI error interrupt enable (PREIEE) bit controls the activation of the interrupt
(INTB) output. When PREIEE is set to logic 1, the PREIEI pending interrupt will assert the
interrupt (INTB) output. When PREIEE is set to logic 0, the PREIEI pending interrupt will
not assert the interrupt (INTB) output.
S/UNI-2488 Telecom Standard Product Datasheet
Released
282
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