PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 127

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Register 0001H: S/UNI-2488 Master Reset, Configuration, and Loopback
This register allows the configuration of S/UNI-2488 features.
PL3EN
WCIMODE
PDLE
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The POS-PHY Level 3 Select bit (PL3EN) is OR’ed with the POSL3_UL3B pin to select
POS-PHY Level 3 mode on the system interface. When PL3EN or POSL3_UL3B are logic
1, the system bus operates in POS-PHY Level 3 mode. When both PL3EN and
POSL3_UL3B are logic 0, the bus operates as a UTOPIA Level 3™ bus. Reading this bit
gives the mode of the bus, (i.e., the OR of the pin and the bit). The default state of this
register bit is logic 0.
The write on clear interrupt mode (WCIMODE) bit selects the clear interrupt mode. When a
logic 1 is written to WCIMODE, the clear interrupt mode is clear on write. When a logic 0 is
written to WCIMODE, the clear interrupt mode is clear on read.
The Parallel Diagnostic Loopback, PDLE bit enables the S/UNI-2488 diagnostic loopback
where the STLI block is directly connected to its SRLI block. When PDLE is logic one,
loopback is enabled. Under this operating condition, the S/UNI-2488 continues to operate
normally in the transmit direction. When PDLE is logic zero, the S/UNI-2488 operates
normally.
R/W
R/W
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
DRESET
ARESET_APS
ARESET_LINE
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
XCONNECTMODE
APSMUX_RCFP
APSMUX_T8TE
APSMUX_TRMP
PDLE
WCIMODE
PL3EN
S/UNI-2488 Telecom Standard Product Datasheet
Default
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
Released
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