PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 497

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Register 2000H: S/UNI-2488 Master Test
This register is used to enable S/UNI-2488 test features. All bits, except PMCTST, PMCATST
and BYPASS are reset to zero by a reset of the S/UNI-2488 using the RSTB input. PMCTST,
PMCATST, and BYPASS are reset when CSB is logic 1. PMCTST, and PMCATST can also be
reset by writing a logic 0 to the corresponding register bit.
Both PMCATST and PMCATST_2488 (bit 5 and 6) in this register must be set to high for OC48
line side analog test.
Access to this register is not affected by the Test Mode Address Force functions in registers
2001H and 2002H.
HIZIO, HIZDATA
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The HIZIO and HIZDATA bits control the tri-state modes of the S/UNI-2488 . While the
HIZIO bit is a logic one, all output pins of the S/UNI-2488 except the data bus and output
TDO are held tri-state. The microprocessor interface is still active. While the HIZDATA bit
is a logic one, the data bus is also held in a high-impedance state which inhibits
microprocessor read cycles. The HIZDATA bit is overridden by the DBCTRL bit.
Type
W
W
W
W
W
R/W
W
Unused
Unused
Unused
Unused
Unused
Unused
PMCATST_2488
PMCATST
PMCTST
Reserved
Reserved
HIZDATA
HIZIO
Function
Unused
Unused
Unused
S/UNI-2488 Telecom Standard Product Datasheet
Default
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
Released
497