PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 407

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
FLUSH
RWB
BUSY
This is a write-only indirect-access register bit used to discard all the current data in a
specified FIFO. Typically, this should be used if a non-empty FIFO needs to be reconfigured.
Note that the RWB bit (bit 14 in this register) must be written to logic 0, and the PHYID set
to all-zeros, at the same time as the FLUSH bit is set to logic 1. The user should then poll the
EMPTY bit (bit 15 in this register) until it is logic 1, which indicates that the FLUSH is
complete. The FLUSH bit must then be cleared to logic 0 before data can be passed to the
TXSDQ. See Section 13.19 for the procedure to access indirect register bits.
This bit is used to indicate whether the user is writing the setup of a FIFO, or reading all
setup information of a FIFO. This bit is used in conjunction with the BUSY bit. When this
bit is set to 1, all the available setup information of the FIFO requested in PHYID[5:0] is
available in the registers TXSDQ FIFO Indirect Configuration, TXSDQ FIFO Indirect Data
Available Threshold, and TXSDQ FIFO Indirect Cells and Packets Count. When this bit is
set to 0, the user is writing the configuration of a FIFO.
This is a read-only bit is used to indicate to the user that the information requested for the
FIFO specified in bits PHYID[5:0] is in the process of being updated. If BUSY is sampled 1,
the update is in progress. If BUSY is sampled 0, the information for the FIFO is available in
the accessed register.
S/UNI-2488 Telecom Standard Product Datasheet
Released
407