PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 177

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
LAIS3
LRDI3
SBIPEACCBLK
LBIPEACCBLK
LREIBLK
The line alarm indication signal detection (LAIS3) bit selects the Line AIS detection
algorithm. When LAIS3 is set to logic 1, Line AIS is declared when a 111 pattern is detected
in bits 6,7,8 of the K2 byte for three consecutive frames. When LAIS3 is set to logic 0, Line
AIS is declared when a 111 pattern is detected in bits 6,7,8 of the K2 byte for five
consecutive frames.
The line remote defect indication detection (LRDI3) bit selects the Line RDI detection
algorithm. When LRDI3 is set to logic 1, Line RDI is declared when a 110 pattern is detected
in bits 6,7,8 of the K2 byte for three consecutive frames. When LRDI3 is set to logic 0, Line
RDI is declared when a 110 pattern is detected in bits 6,7,8 of the K2 byte for five
consecutive frames.
The section BIP error accumulation block (SBIPEACCBLK) bit controls the accumulation of
section BIP errors. When SBIPEACCBLK is set to logic 1, the section BIP accumulation
represents BIP-8 block errors (a maximum of 1 error per frame). When SBIPEACCBLK is
set to logic 0, the section BIP accumulation represents BIP-8 errors (a maximum of 8 errors
per frame).
The line BIP error accumulation block (LBIPEACCBLK) bit controls the accumulation of
line BIP errors. When LBIPEACCBLK is set to logic 1, the line BIP accumulation represents
BIP-24 block errors (a maximum of 1 error per STS-3/STM-1 per frame). When
LBIPEACCBLK is set to logic 0, the line BIP accumulation represents BIP-8 errors (a
maximum of 8 errors per STS-1/STM-0 per frame).
The line REI block (LREIBLK) bit controls the extraction of line REI errors from the M1
byte. When LREIBLK is set to logic 1, the extracted line REI are interpreted as block BIP-24
errors (a maximum of 1 error per STS-3/STM-1 per frame). When LREIBLK is set to logic
0, the extracted line REI are interpreted as BIP-8 errors (a maximum of 8 errors per STS-
1/STM-0 per frame).
S/UNI-2488 Telecom Standard Product Datasheet
Released
177