PM5366-PI PMC-Sierra, Inc., PM5366-PI Datasheet - Page 96

• Manufacturer Part Number: PM5366-PI
• Description: HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER AND M13 MULTIPLEXER
• Manufacturer: PMC-Sierra, Inc.

PRELIMINARY
DATASHEET
PMC-2010672
9.13.1 DS3 Bit Oriented Code Generation
9.13.2 DS3 Transmitter Timing Sources
PROPRIETARY AND CONFIDENTIAL
A valid pair of P-bits is automatically calculated and inserted by the DS3-TRAN.
When C-bit parity mode is selected, the path parity bits, and far end block error
(FEBE) indications are automatically inserted.
When enabled for C-bit parity operation, the FEAC channel is sourced by the bit-
oriented code transmitter. The path maintenance data link messages are
sourced by the TDPR data link transmitter.
The DS3-TRAN supports diagnostic modes in which it inserts parity or path parity
errors, F-bit framing errors, M-bit framing errors, invalid X or P-bits, line code
violations, or all-zeros.
63 of the possible 64 bit oriented codes may be transmitted in the DS3 C-bit
parity Far-End Alarm and Control (FEAC) channel. The 64 th code (111111) is
similar to the HDLC Flag sequence and is used to disable transmission of any bit
oriented codes. When transmission is disabled the FEAC channel is set to all
ones.
Bit oriented codes are transmitted on the DS3 Far-End Alarm and Control
channel as a 16-bit sequence consisting of 8 ones, a zero, 6 code bits, and a
trailing zero (111111110xxxxxx0) which is repeated as long as the code is not
111111. The code to be transmitted is programmed by writing to the XBOC code
registers when it is held until the latest code has been transmitted at least 10
times. An interrupt or polling mechanism is used to determine when the most
recent code written the XBOC register is being transmitted and a new code can
be accepted.
DS3 transmitter timing has three possible sources:
1.
2.
TICLK[3:1] input pins. If the system interface is SBI, then TEMAP-84 is
Integral DS3 clock synthesizer, which generates a gapped DS3 clock
the SBI bus clock master, and uses the SAJUST_REQ output signal to
issue timing justification requests to the link-layer device. If the system
interface is serial clock and data, TEMAP-84 derives TGAPCLK[3:1]
from TICLK[3:1].)
from the CLK52M input pin, in response to SBI bus timing justification
requests from the link-layer device. TEMAP-84 is the SBI bus clock
slave in this mode, and the SBI bus must be the system side option.
ISSUE 1
84
HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER
AND M13 MULTIPLEXER
PM5366 TEMAP-84