PM5366-PI PMC-Sierra, Inc., PM5366-PI Datasheet - Page 94

• Manufacturer Part Number: PM5366-PI
• Description: HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER AND M13 MULTIPLEXER
• Manufacturer: PMC-Sierra, Inc.

PRELIMINARY
DATASHEET
PMC-2010672
9.11 DS3/E3 HDLC Receiver (RDLC)
9.12 DS3/E3 Performance Monitor Accumulator (DS3/E3-PMON)
PROPRIETARY AND CONFIDENTIAL
• line code violation (LCV) events
• parity error (PERR) events
containing code values different from the detected code are received in a moving
window of ten code periods.
Valid BOC are indicated through the RBOC Interrupt Status register. The BOC
bits are set to all ones (111111) if no valid code has been detected. An interrupt
is generated to signal when a detected code has been validated, or optionally,
when a valid code goes away (i.e. the BOC bits go to all ones).
The RDLC is a microprocessor peripheral used to receive HDLC frames on the
DS3 C-bit parity Path Maintenance Data Link, E3 G.832 Network Operator byte,
E3 G.832 General Purpose Communications Channel or E3 G.751 National Use
bit.
The RDLC detects the change from flag characters to the first byte of data,
removes stuffed zeros on the incoming data stream, receives packet data, and
calculates the CRC-CCITT frame check sequence (FCS).
In the address matching mode, only those packets whose first data byte matches
one of two programmable bytes or the universal address (all ones) are stored in
the FIFO. The two least significant bits of the address comparison can be
masked for LAPD SAPI matching.
Received data is placed into a 128-byte FIFO buffer. An interrupt is generated
when a programmable number of bytes are stored in the FIFO buffer. Other
sources of interrupt are detection of the terminating flag sequence, abort
sequence, or FIFO buffer overrun.
The Status Register contains bits which indicate the overrun or empty FIFO
status, the interrupt status, and the occurrence of first flag or end of message
bytes written into the FIFO. The Status Register also indicates the abort, flag,
and end of message status of the data just read from the FIFO. On end of
message, the Status Register indicates the FCS status and if the packet
contained a non-integer number of bytes.
The Performance Monitor (PMON) Block interfaces directly with the DS3 Framer
(DS3-FRMR) and E3 Framer. Saturating counters are used to accumulate:
ISSUE 1
82
HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER
AND M13 MULTIPLEXER
PM5366 TEMAP-84