PM5366-PI PMC-Sierra, Inc., PM5366-PI Datasheet - Page 105

• Manufacturer Part Number: PM5366-PI
• Description: HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER AND M13 MULTIPLEXER
• Manufacturer: PMC-Sierra, Inc.

PRELIMINARY
DATASHEET
PMC-2010672
9.20.1 E3 Transmitter Timing Sources
PROPRIETARY AND CONFIDENTIAL
• inserts the General Purpose Communication Channel (GC) byte from the TDPR
• inserts the Remote Alarm Indication bit (bit 11 of the frame) either via a register
• inserts the National Use reserved bit (bit 12 of the frame) either as a fixed value
• optionally identifies the tributary justification bits and stuff opportunity bits as
block when the TNETOP bit in the E3 Data Link Control register is logic 0;
otherwise, the byte is set to all ones.
In G.751 E3 mode, the E3-TRAN :
bit or, optionally, when the E3-FRMR declares OOF;
through a register bit or from the HDLC transmitter as configured by the TNETOP
bit in the E3 Data Link Control register and the NATUSE bit in the E3 TRAN
Configuration register;
either overhead or payload for payload mappings that take advantage of the full
bandwidth.
Further, the E3-TRAN can provide insertion of bit errors in the framing pattern or
in the parity bits, and insertion of single line code violations for diagnostic
purposes.
E3 transmitter timing has three possible sources:
1.
2.
3.
TICLK[3:1] input pins. If the system interface is SBI, then TEMAP-84 is
Integral E3 clock synthesizer, which generates a gapped E3 clock from
Recovered E3 clock from the RCLK[3:1] input pins. If the system
the SBI bus clock master, and uses the SAJUST_REQ output signal to
issue timing justification requests to the link-layer device. If the system
interface is serial clock and data, TEMAP-84 derives TGAPCLK[3:1]
from TICLK[3:1].)
the CLK52M input pin, in response to SBI bus timing justification
requests from the link-layer device. TEMAP-84 is the SBI bus clock
slave in this mode, and the SBI bus must be the system side option.
External jitter attenuation is recommended when using this E3 timing
option.
interface is SBI, then TEMAP-84 is the SBI bus clock master, as in case
1 above. If the system interface is serial clock and data, TEMAP-84
derives TGAPCLK[3:1] from the recovered E3 clock.)
ISSUE 1
93
HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER
AND M13 MULTIPLEXER
PM5366 TEMAP-84