PM5366-PI PMC-Sierra, Inc., PM5366-PI Datasheet - Page 16
![no-image](/images/no-image-200.jpg)
PM5366-PI
Manufacturer Part Number
PM5366-PI
Description
HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER AND M13 MULTIPLEXER
Manufacturer
PMC-Sierra, Inc.
Datasheet
1.PM5366-PI.pdf
(267 pages)
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PRELIMINARY
DATASHEET
PMC-2010672
PROPRIETARY AND CONFIDENTIAL
• Provides performance monitoring counters sufficiently large as to allow
• An unframed pseudo-random sequence user selectable from 2
• Line side interface is either from the DS3 interface via the M13 multiplex or from
• Frames in the presence of and detects the “Japanese Yellow” alarm.
• Provides non-intrusive performance monitoring of either ingress or egress paths,
• Frames to ITU-T G.704 basic and CRC-4 multiframe formatted E1 signals. The
• Provides performance monitoring counters sufficiently large as to allow
• An unframed pseudo-random sequence user selectable from 2
• May be timed to its associated receive clock (loop timing) or may derive its timing
• Provides a digital phase locked loop for generation of a low jitter transmit clock.
performance monitor counter polling at a minimum rate of once per second.
Optionally, updates the performance monitoring counters and interrupts the
microprocessor once per second.
1 or 2
directions. The detector counts pattern errors using a 16-bit non-saturating PRBS
error counter.
the SONET/SDH Drop bus via the VT1.5, TU-11, VT2 or TU-12 demapper.
Each one of 63 E1 performance monitor sections:
as selected on a per-tributary basis.
framing procedures are consistent ITU-T G.706 specifications.
• Non-intrusive performance monitoring provided by the TEMAP-84 also
performance monitor counter polling at a minimum rate of once per second.
Optionally, updates the performance monitoring counters and interrupts the
microprocessor once per second.
1 or 2
directions. The detector counts pattern errors using a 16-bit non-saturating PRBS
error counter.
Each one of 84 transmit tributaries:
from a common egress clock or a common transmit clock; the transmit line clock
may be synthesized from an N*8 kHz reference.
provides an HDLC interface with 128 bytes of buffering for terminating the
facility data link in either the ingress or egress paths, as selected on a per-
tributary basis.
20
20
–1, may be detected in the T1 stream in either the ingress or egress
–1, may be detected in the E1 stream in either the ingress or egress
ISSUE 1
4
HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER
7
7
–1, 2
–1, 2
AND M13 MULTIPLEXER
PM5366 TEMAP-84
11
11
–1, 2
–1, 2
15
15
–
–
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