PM5366-PI PMC-Sierra, Inc., PM5366-PI Datasheet - Page 122

• Manufacturer Part Number: PM5366-PI
• Description: HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER AND M13 MULTIPLEXER
• Manufacturer: PMC-Sierra, Inc.

PRELIMINARY
DATASHEET
PMC-2010672
9.32.1 DS3 Mapper Serializer
9.32.2 DS3 Mapper Elastic Store
9.32.3 DS3 Synchronizer
PROPRIETARY AND CONFIDENTIAL
channel bits. Fixed stuff bytes are used to fill the remaining bytes. Please refer
to section 9.27 for a description of the DS3 mapping.
High speed serial data from the DS3-TRAN block is deserialized and written into
the Elastic Store.
The elastic store block is provided to compensate for frequency differences
between the DS3 stream from the DS3-TRAN block and the STS-1 (STM-0/AU3)
SPE capacity. The DS3 Serializer writes data into the elastic store at the
TICLK/8 rate while data is read out at the stuffed STS-1 (STM-0/AU3) byte rate.
If an overflow or underflow condition occurs, an interrupt is optionally asserted
and the Elastic Store read and write address are reset to the startup values
(logically 180 degrees apart).
The Elastic store is 128 bits (16 bytes) to allow for a fixed read/write pointer lag
of 7 bytes (3 bytes for TOH, 1 byte for POH, 2 bytes for R bits, and 3 overhead
bits which is rounded-up to 1 byte). Four bytes are also added on either side for
positive and negative threshold detection.
The DS3 Synchronizer performs the mapping of the DS3 into the STS-1
(STM-0/AU3) SPE. The DS3 Synchronizer monitors the Elastic Store level to
control the stuffing algorithm to avoid overflow (i.e. run faster) and underflow
(i.e. run slower) conditions. The fill level of the elastic store is monitored and
stuff opportunities in the DS3 mapping are used to center the Elastic Store. To
consume a stuff opportunity, the five C-bits on a row are set to ones and the S bit
is used to carry an DS3 information bit. When the S bit is not used to carry
information, the C-bits on the row are set to zeros.
The DS3 synchronizer uses a fixed bit leaking algorithm which leaks 8 bits of
phase buildup in 500 µs. The 8 kHz STS-1 (STM-0/AU3) frame interval is
subdivided into 9 rows. Each row contains one stuff opportunity. Table 8
illustrates the stuffing implementation where S means stuff bit and I means an
information bit (DS3 data).
ISSUE 1
110
HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER
AND M13 MULTIPLEXER
PM5366 TEMAP-84