A43L0616V-8 AMIC Technology, Corp., A43L0616V-8 Datasheet - Page 35

• Manufacturer Part Number: A43L0616V-8
• Description: 512K x 16 Bit x 2 Banks Synchronous DRAM
• Manufacturer: AMIC Technology, Corp.

CLOCK
A10/AP
ADDR
Write Interrupted by Precharge Command & Write Burst Stop Cycle (@ Burst Length = Full Page)
(October, 1999, Version 0.0)
CKE
RAS
CAS
DQM
CS
BA
DQ
WE
0
Row Active
(A-Bank)
* Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible.
RAa
RAa
1
2. Data-in at the cycle of burst stop command cannot be written into corresponding memory cell.
3. Data-in at the cycle of interrupted by precharge cannot be written into the corresponding memory cell.
4. Burst stop is valid only at every burst length.
It is defined by AC parameter of tBDL(=1CLK).
It is defined by AC parameter of tRDL(1=CLK).
DQM at write interrupted by precharge command is needed to ensure tRDL of 1CLK.
DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.
Input data after Row precharge cycle will be masked internally.
2
3
(A-Bank)
* Note 1
Write
DAa0
CAa
4
DAa1 DAa2
5
6
DAa3
7
DAa4
* Note 2
8
t
Burst Stop
BDL
9
High
34
10
* Note 1
(A-Bank)
DAb0 DAb1 DAb2 DAb3
Write
CAb
11
12
13
14
DAb4 DAb5
AMIC Technology, Inc.
15
* Note 3
16
t
RDL
Precharge
(A-Bank)
17
A43L0616
: Don't care
18
19