A43L0616V-8 AMIC Technology, Corp., A43L0616V-8 Datasheet - Page 27

• Manufacturer Part Number: A43L0616V-8
• Description: 512K x 16 Bit x 2 Banks Synchronous DRAM
• Manufacturer: AMIC Technology, Corp.

(October, 1999, Version 0.0)
Page Read & Write Cycle at Same Bank @Burst Length=4
CLOCK
A10/AP
ADDR
(CL=2)
(CL=3)
CKE
RAS
CAS
DQM
CS
DQ
DQ
BA
WE
*Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write
0
Row Active
(A-Bank)
2. Row precharge will interrupt writing. Last data input, t
3. DQM should mask invalid input data on precharge command cycle when asserting precharge
Ra
Ra
command to avoid bus contention.
before end of burst. Input data after Row precharge cycle will be masked internally.
1
2
t
RCD
3
(A-Bank)
Ca0
Read
4
5
(A-Bank)
Read
Cb0
Qa0
6
Qa1
Qa0
7
Qb0
Qa1
*Note 2
8
*Note1
Qb0
Qb1
26
RDL
9
High
before Row precharge, will be written.
10
(A-Bank)
Write
Dc0
Dc0
Cc0
11
Dc1
Dc1
12
t
CDL
(A-Bank)
Dd0
Dd0
Write
Cd0
13
Dd1
Dd1
14
AMIC Technology, Inc.
t
RDL
Precharge
*Note3
(A-Bank)
*Note 2
15
16
A43L0616
17
: Don't care
18
19