M50FLW040AK1 STMicroelectronics, M50FLW040AK1 Datasheet - Page 23

• Manufacturer Part Number: M50FLW040AK1
• Description: 4 Mbit (5 x 64KByte Blocks + 3 x 16 x 4KByte Sectors) 3V Supply Firmware Hub / Low Pin Count Flash Memory
• Manufacturer: STMicroelectronics

When the Program Suspend Status bit is ‘0’, the
Program/Erase Controller is active, or has com-
pleted its operation. When the bit is ‘1’, a Program/
Erase Suspend command has been issued and
the memory is waiting for a Program/Erase Re-
sume command.
When a Program/Erase Resume command is is-
sued, the Program Suspend Status bit returns to
‘0’.
Block Protection Status (Bit SR1). The
Protection Status bit can be used to identify if the
Program or Erase operation has tried to modify the
contents of a protected block. When the Block Pro-
tection Status bit is to ‘0’, no Program or Erase op-
erations have been attempted to protected blocks
Table 14. Status Register Bits
Note: 1. For Program operations during Erase Suspend Bit SR6 is ‘1’, otherwise Bit SR6 is ‘0’.
Program active
Program suspended
Program completed successfully
Program failure due to V
Program failure due to Block Protection (FWH/LPC Interface
only)
Program failure due to cell failure
Erase active
Erase suspended
Erase completed successfully
Erase failure due to V
Erase failure due to Block Protection (FWH/LPC Interface
only)
Erase failure due to failed cell(s) in block
PP
PP
Error
Operation
Error
Block
since the last Clear Status Register command or
hardware reset. When the Block Protection Status
bit is ‘1’, a Program or Erase operation has been
attempted on a protected block.
Once it is set to ‘1’, the Block Protection Status bit
can only be reset to ‘0’ by a Clear Status Register
command or by a hardware reset. If it is set to ‘1’,
it should be reset before a new Program or Erase
command is issued, otherwise the new command
will appear to have failed, too.
Using the A/A Mux Interface, the Block Protection
Status bit is always ‘0’.
Reserved (Bit SR0). Bit 0 of the Status Register
is reserved. Its value should be masked.
SR7
‘0’
‘1’
‘1’
‘1’
‘1’
‘0’
‘1’
‘1’
‘1’
‘1’
‘1’
‘1
SR6
X
X
X
X
X
X
‘0’
‘1’
‘0’
‘0’
‘0’
‘0’
(1)
(1)
(1)
(1)
(1)
(1)
M50FLW040A, M50FLW040B
SR5
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘1’
‘1’
‘1’
SR4
‘0’
‘0’
‘0’
‘1’
‘1’
‘1’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
SR3
‘0’
‘0’
‘0’
‘1’
‘0’
‘0’
‘0’
‘0’
‘0’
‘1’
‘0’
‘0’
SR2
‘0’
‘1’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
SR1
23/52
‘0’
‘0’
‘0’
‘0’
‘1’
‘0’
‘0’
‘0’
‘0’
‘0’
‘1’
‘0’