M50FLW040AK1 STMicroelectronics, M50FLW040AK1 Datasheet - Page 14

• Manufacturer Part Number: M50FLW040AK1
• Description: 4 Mbit (5 x 64KByte Blocks + 3 x 16 x 4KByte Sectors) 3V Supply Firmware Hub / Low Pin Count Flash Memory
• Manufacturer: STMicroelectronics

M50FLW040A, M50FLW040B
Table 6. FWH Bus Read Field Definitions
Figure 7. FWH Bus Read Waveforms
14/52
Number
previous
previous
Clock
Cycle
13-14
16-17
3-9
+1
+1
10
11
12
15
1
2
CLK
FWH4
FWH0-FWH3
Number of
clock cycles
Count
Clock
Cycle
M=2n
1
1
7
1
1
1
2
1
1
1
WSYNC
RSYNC
START
MSIZE
IDSEL
ADDR
Field
DATA
TAR
TAR
TAR
TAR
START
1
FWH0-
FWH3
1101b
1111b
1111b
0101b
0000b
1111b
1111b
XXXX
XXXX
XXXX
XXXX
(float)
(float)
IDSEL
1
Memory
N/A
I/O
O
O
O
O
O
I
I
I
I
I
ADDR
7
On the rising edge of CLK with FWH4 Low, the contents of FWH0-
FWH3 indicate the start of a FWH Read cycle.
Indicates which FWH Flash Memory is selected. The value on
FWH0-FWH3 is compared to the IDSEL strapping on the FWH
Flash Memory pins to select which FWH Flash Memory is being
addressed.
A 28-bit address is transferred, with the most significant nibble
first. For the multi-byte read operation, the least significant bits
(MSIZE of them) are treated as Don’t Care, and the read operation
is started with each of these bits reset to 0. Address lines A19-21
and A23-27 are treated as Don’t Care during a normal memory
array access, with A22=1, but are taken into account for a register
access, with A22=0. (See
This one clock cycle is driven by the host to determine the number
of Bytes that will be transferred. M50FLW040 supports: single
Byte transfer (0000b), 2-Byte transfer (0001b), 4-Byte transfer
(0010b), 16-Byte transfer (0100b) and 128-Byte transfer (0111b).
The host drives FWH0-FWH3 to 1111b to indicate a turnaround
cycle.
The FWH Flash Memory takes control of FWH0-FWH3 during this
cycle.
The FWH Flash Memory drives FWH0-FWH3 to 0101b (short
wait-sync) for two clock cycles, indicating that the data is not yet
available. Two wait-states are always included.
The FWH Flash Memory drives FWH0-FWH3 to 0000b, indicating
that data will be available during the next clock cycle.
Data transfer is two CLK cycles, starting with the least significant
nibble. If multi-Byte read operation is enabled, repeat cycle-16 and
cycle-17 n times, where n = 2
The FWH Flash Memory drives FWH0-FWH3 to 1111b to indicate
a turnaround cycle.
The FWH Flash Memory floats its outputs, the host takes control
of FWH0-FWH3.
MSIZE
1
TAR
2
Table
Description
SYNC
3
MSIZE
15.)
.
DATA
M
TAR
2
AI08433B