M50FLW040AK1 STMicroelectronics, M50FLW040AK1 Datasheet - Page 13

• Manufacturer Part Number: M50FLW040AK1
• Description: 4 Mbit (5 x 64KByte Blocks + 3 x 16 x 4KByte Sectors) 3V Supply Firmware Hub / Low Pin Count Flash Memory
• Manufacturer: STMicroelectronics

See
ure
each clock cycle of the transfer. See
and
nals.
Bus Abort. The Bus Abort operation can be used
to abort the current bus operation immediately. A
Bus Abort occurs when FWH4/LFRAME is driven
Low, V
puts the
FWH0/LAD0-FWH3/LAD3, to high impedance.
Note that, during a Bus Write operation, the Com-
mand Interface starts executing the command as
soon as the data is fully received. A Bus Abort dur-
ing the final TAR cycles is not guaranteed to abort
the command. The bus, however, will be released
immediately.
Standby. When FWH4/LFRAME is High, V
device is put into Standby mode, where FWH0/
LAD0-FWH3/LAD3 are put into a high-impedance
state and the Supply Current is reduced to the
Standby level, I
Reset. During the Reset mode, all internal circuits
are switched off, the device is deselected, and the
outputs are put to high-impedance. The device is
in the Reset mode when Interface Reset, RP, or
CPU Reset, INIT, is driven Low, V
must be held Low, V
verts to the Read mode upon return from the Re-
set mode, and the Lock Registers return to their
default states regardless of their states before Re-
set. If RP or INIT goes Low, V
or Erase operation, the operation is aborted and
the affected memory cells no longer contain valid
data. The device can take up to t
Program or Erase operation.
Block Protection. Block
forced using the signals Top Block Lock, TBL, and
Write Protect, WP, regardless of the state of the
Lock Registers.
Address/Address Multiplexed (A/A Mux) Bus
Operations
The Address/Address Multiplexed (A/A Mux) Inter-
face has a more traditional-style interface. The sig-
nals consist of a multiplexed address signals (A0-
A10), data signals, (DQ0-DQ7) and three control
signals (RC, G, W). An additional signal, RP, can
be used to reset the memory.
10., for a description of the Field definitions for
Figure
Table 7.
IL
, during the bus operation. The device
15., for details on the timings of the sig-
Input/Output
and
CC1
Table
.
IL
, for t
9., and
Communication
PLPH
Protection
IL
, during a Program
Figure 8.
. The memory re-
PLRH
IL
. RP or INIT
Table
to abort a
can
and
IH
pins,
, the
Fig-
26.,
be
The Address/Address Multiplexed (A/A Mux) Inter-
face is included for use by Flash Programming
equipment for faster factory programming. Only a
subset of the features available to the Firmware
Hub (FWH)/Low Pin Count (LPC) Interface are
available; these include all the Commands but ex-
clude the Security features and other registers.
The following operations can be performed using
the appropriate bus cycles: Bus Read, Bus Write,
Output Disable and Reset.
When the Address/Address Multiplexed (A/A Mux)
Interface is selected, all the blocks are unprotect-
ed. It is not possible to protect any blocks through
this interface.
Bus Read. Bus Read operations are used to read
the contents of the Memory Array, the Electronic
Signature or the Status Register. A valid Bus Read
operation begins by latching the Row Address and
Column Address signals into the memory using
the Address Inputs, A0-A10, and the Row/Column
Address Select RC. Write Enable (W) and Inter-
face Reset (RP) must be High, V
Enable, G, Low, V
output the value, according to the timing con-
straints specified in
Bus Write. Bus Write operations are used to write
to the Command Interface. A valid Bus Write oper-
ation begins by latching the Row Address and Col-
umn Address signals into the memory using the
Address Inputs, A0-A10, and the Row/Column Ad-
dress Select RC. The data should be set up on the
Data Inputs/Outputs; Output Enable, G, and Inter-
face Reset, RP, must be High, V
able, W, must be Low, V
Outputs are latched on the rising edge of Write En-
able, W. See
of the timing requirements.
Output Disable. The data outputs are high-im-
pedance when the Output Enable, G, is at V
Reset. During the Reset mode, all internal circuits
are switched off, the device is deselected, and the
outputs are put at high-impedance. The device is
in the Reset mode when RP is Low, V
be held Low, V
during a Program or Erase operation, the opera-
tion is aborted, and the affected memory cells no
longer contain valid data. The memory can take up
to t
PLRH
to abort a Program or Erase operation.
Figure
M50FLW040A, M50FLW040B
IL
for t
IL
. The Data Inputs/Outputs will
Figure
18., and
PLPH
17., and
. If RP goes Low, V
IL
Table
. The Data Inputs/
IH
; and Write En-
IH
29., for details
Table
, and Output
IL
. RP must
28..
IH
13/52
.
IL
,