M50FLW040AK1 STMicroelectronics, M50FLW040AK1 Datasheet - Page 11

• Manufacturer Part Number: M50FLW040AK1
• Description: 4 Mbit (5 x 64KByte Blocks + 3 x 16 x 4KByte Sectors) 3V Supply Firmware Hub / Low Pin Count Flash Memory
• Manufacturer: STMicroelectronics

changed during Program or Erase Suspend, and
care should be taken to avoid this.
Write Protect (WP). The Write Protect input is
used to prevent the Main Blocks (Blocks 0 to 6)
from being changed. When Write Protect, WP, is
driven Low, V
the Main Blocks have no effect, regardless of the
state of the Lock Register. When Write Protect,
WP, is driven High, V
is determined by the Lock Register. The state of
Write Protect, WP, does not affect the protection of
the Top Block (Block 7). For details, see
DIX
Write Protect, WP, must be set prior to a Program
or Erase operation is initiated, and must not be
changed until the operation has completed other-
wise unpredictable results may occur. Similarly,
unpredictable behavior is possible if WP is
changed during Program or Erase Suspend, and
care should be taken to avoid this.
Reserved for Future Use (RFU). These pins do
not presently have assigned functions. They must
be left disconnected, except for ID3 (when in LPC
mode) which can be left connected. The electrical
characteristics for this signal are as described in
the
Address/Address Multiplexed (A/A Mux)
Signal Descriptions
Please see
Address Inputs (A0-A10). The Address Inputs
are used to set the Row Address bits (A0-A10) and
the Column Address bits (A11-A18). They are
latched during any bus operation by the Row/Col-
umn Address Select input, RC.
Data Inputs/Outputs (DQ0-DQ7). The Data In-
puts/Outputs hold the data that is to be written to
or read from the memory. They output the data
stored at the selected address during a Bus Read
operation. During Bus Write operations they carry
the commands that are sent to the Command In-
terface of the internal state machine. The Data In-
puts/Outputs, DQ0-DQ7, are latched during a Bus
Write operation.
Output Enable (G). The Output Enable signal, G,
controls the output buffers during a Bus Read op-
eration.
Write Enable (W). The Write Enable signal, W,
controls the Bus Write operation of the Command
Interface.
Row/Column Address Select (RC). The
Column Address Select input selects whether the
Address Inputs are to be latched into the Row Ad-
“Identification Inputs
A..
Figure 3.
IL
, Program and Erase operations in
IH
and
, the protection of the Block
(ID0-ID3).” section.
Table
2..
APPEN-
Row/
dress bits (A0-A10) or the Column Address bits
(A11-A18). The Row Address bits are latched on
the falling edge of RC whereas the Column Ad-
dress bits are latched on its rising edge.
Ready/Busy Output (RB). The Ready/Busy pin
gives the status of the device’s Program/Erase
Controller. When Ready/Busy is Low, V
vice is busy with a program or erase operation,
and it will not accept any additional program or
erase command (except for the Program/Erase
Suspend command). When Ready/Busy is High,
V
erase operation.
Supply Signal Descriptions
The Supply Signals are the same for both interfac-
es.
V
supplies the power for all operations (read, pro-
gram, erase, etc.).
The Command Interface is disabled when the V
Supply Voltage is less than the Lockout Voltage,
V
accidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time, the operation aborts, and the memory
contents that were being altered will be invalid. Af-
ter V
reset to Read mode.
A 0.1µF capacitor should be connected between
the V
pin to decouple the current surges from the power
supply. Both V
connected to the power supply. The PCB track
widths must be sufficient to carry the currents re-
quired during program and erase operations.
V
Supply Voltage pin is used to select the Fast Pro-
gram (see the Quadruple Byte Program command
description in A/A Mux interface and the Double/
Quadruple Byte Program command description in
FWH mode) and Fast Erase options of the memo-
ry.
When V
take place as normal. When V
gram and Erase operations are used. Any other
voltage input to V
ior, and should not be used.
V
80 hours during the life of the memory.
V
age measurements.
OH
CC
LKO
PP
PP
SS
, the memory is ready for any read, program or
Optional Supply Voltage. The V
Ground. V
Supply Voltage. The V
CC
. This is to prevent Bus Write operations from
should not be set to V
CC
becomes valid, the Command Interface is
PP
Supply Voltage pins and the V
= V
CC
M50FLW040A, M50FLW040B
CC
SS
PP
, program and erase operations
is the reference for all the volt-
Supply Voltage pins must be
will result in undefined behav-
PP
CC
PPH
= V
Supply Voltage
for more than
PPH
PP
SS
OL
, Fast Pro-
Optional
, the de-
Ground
11/52
CC