M50FLW040AK1 STMicroelectronics, M50FLW040AK1 Datasheet - Page 16

• Manufacturer Part Number: M50FLW040AK1
• Description: 4 Mbit (5 x 64KByte Blocks + 3 x 16 x 4KByte Sectors) 3V Supply Firmware Hub / Low Pin Count Flash Memory
• Manufacturer: STMicroelectronics

M50FLW040A, M50FLW040B
Table 8. LPC Bus Read Field Definitions (1-Byte)
Figure 9. LPC Bus Read Waveforms (1-Byte)
16/52
Clock Cycle
Number
13-14
16-17
3-10
11
12
15
18
19
1
2
CLK
LFRAME
LAD0-LAD3
Number of
clock cycles
Count
Clock
Cycle
1
1
8
1
1
2
1
2
1
1
CYCTYPE
WSYNC
RSYNC
START
ADDR
+ DIR
Field
DATA
TAR
TAR
TAR
TAR
START
1
CYCTYPE
LAD0-
0000b
0100b
1111b
1111b
0101b
0000b
1111b
1111b
XXXX
XXXX
+ DIR
LAD3
(float)
(float)
1
ADDR
Memory
8
N/A
I/O
O
O
O
O
O
I
I
I
I
TAR
On the rising edge of CLK with LFRAME Low, the contents
of LAD0-LAD3 must be 0000b to indicate the start of a
LPC cycle.
Indicates the type of cycle and selects 1-byte reading. Bits
3:2 must be 01b. Bit 1 indicates the direction of transfer: 0b
for read. Bit 0 is Don’t Care.
A 32-bit address is transferred, with the most significant
nibble first. A23-A31 must be set to 1. A22=1 for memory
access, and A22=0 for register access.
appropriate values for A21-A19.
The host drives LAD0-LAD3 to 1111b to indicate a
turnaround cycle.
The LPC Flash Memory takes control of LAD0-LAD3
during this cycle.
The LPC Flash Memory drives LAD0-LAD3 to 0101b
(short wait-sync) for two clock cycles, indicating that the
data is not yet available. Two wait-states are always
included.
The LPC Flash Memory drives LAD0-LAD3 to 0000b,
indicating that data will be available during the next clock
cycle.
Data transfer is two CLK cycles, starting with the least
significant nibble.
The LPC Flash Memory drives LAD0-LAD3 to 1111b to
indicate a turnaround cycle.
The LPC Flash Memory floats its outputs, the host takes
control of LAD0-LAD3.
2
SYNC
3
DATA
2
Description
TAR
2
AI04429
Table 5.
shows the