M50FLW040AK1 STMicroelectronics, M50FLW040AK1 Datasheet - Page 15

• Manufacturer Part Number: M50FLW040AK1
• Description: 4 Mbit (5 x 64KByte Blocks + 3 x 16 x 4KByte Sectors) 3V Supply Firmware Hub / Low Pin Count Flash Memory
• Manufacturer: STMicroelectronics

Table 7. FWH Bus Write Field Definitions
Figure 8. FWH Bus Write Waveforms
Number
previous
previous
previous
previous
previous
Clock
Cycle
11-18
3-9
+1
+1
+1
+1
+1
10
1
2
CLK
FWH4
FWH0-FWH3
Number of
clock cycles
M=2/4/8
Count
Clock
Cycle
1
1
7
1
1
1
1
1
1
START
MSIZE
IDSEL
ADDR
SYNC
Field
DATA
TAR
TAR
TAR
TAR
START
1
FWH0-
FWH3
1110b
1111b
1111b
0000b
1111b
1111b
XXXX
XXXX
XXXX
XXXX
(float)
(float)
IDSEL
1
Memory
N/A
I/O
O
O
O
I
I
I
I
I
I
ADDR
7
On the rising edge of CLK with FWH4 Low, the contents of
FWH0-FWH3 indicate the start of a FWH Write Cycle.
Indicates which FWH Flash Memory is selected. The value on
FWH0-FWH3 is compared to the IDSEL strapping on the FWH
Flash Memory pins to select which FWH Flash Memory is being
addressed.
A 28-bit address is transferred, with the most significant nibble
first. Address lines A19-21 and A23-27 are treated as Don’t
Care during a normal memory array access, with A22=1, but are
taken into account for a register access, with A22=0. (See
15.)
0000(Single Byte Transfer) 0001 (Double Byte Transfer) 0010b
(Quadruple Byte Transfer).
Data transfer is two cycles, starting with the least significant
nibble. (The first pair of nibbles is that at the address with A1-
A0 set to 00, the second pair with A1-A0 set to 01, the third
pair with A1-A0 set to 10, and the fourth pair with A1-A0 set
to 11. In Double Byte Program the first pair of nibbles is that at
the address with A0 set to 0, the second pair with A0 set to 1)
The host drives FWH0-FWH3 to 1111b to indicate a turnaround
cycle.
The FWH Flash Memory takes control of FWH0-FWH3 during
this cycle.
The FWH Flash Memory drives FWH0-FWH3 to 0000b,
indicating it has received data or a command.
The FWH Flash Memory drives FWH0-FWH3 to 1111b,
indicating a turnaround cycle.
The FWH Flash Memory floats its outputs and the host takes
control of FWH0-FWH3.
MSIZE
1
DATA
M
M50FLW040A, M50FLW040B
TAR
Description
2
SYNC
1
TAR
2
AI08434B
Table
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