M50FLW040AK1 STMicroelectronics, M50FLW040AK1 Datasheet - Page 19

• Manufacturer Part Number: M50FLW040AK1
• Description: 4 Mbit (5 x 64KByte Blocks + 3 x 16 x 4KByte Sectors) 3V Supply Firmware Hub / Low Pin Count Flash Memory
• Manufacturer: STMicroelectronics

Once the command is issued, subsequent Bus
Read operations read the value in the Status Reg-
ister. (See the section on the Status Register for
details on the definitions of the Status Register
bits.)
If the address falls in a protected block, the Pro-
gram operation will abort, the data in the memory
array will not be changed, and the Status Register
will indicate the error.
During the Program operation, the memory will
only accept the Read Status Register command
and the Program/Erase Suspend command. All
other commands are ignored.
See
the Program command. Typical Program times are
given in
Quadruple Byte Program Command (A/A Mux
Interface). The Quadruple Byte Program Com-
mand is used to program four adjacent Bytes in
the memory array at a time. The four Bytes must
differ only for addresses A0 and A1. Programming
should not be attempted when V
Five Bus Write operations are required to issue the
command. The second, third and fourth Bus Write
cycles latch the respective addresses and data of
the first, second and third Bytes in the Program/
Erase Controller. The fifth Bus Write cycle latches
the address and data of the fourth Byte and starts
the Program/Erase Controller. Once the command
is issued, subsequent Bus Read operations read
the value in the Status Register. (See the section
on the Status Register for details on the definitions
of the Status Register bits.)
During the Quadruple Byte Program operation, the
memory will only accept the Read Status Register
and Program/Erase Suspend commands. All other
commands are ignored.
Note that the Quadruple Byte Program command
cannot change a bit set to ‘0’ back to ‘1’ and at-
tempting to do so will not modify its value. One of
the erase commands must be used to set all of the
bits in the block to ‘1’.
See
the Quadruple Byte Program command. Typical
Quadruple Byte Program times are given in
18..
Double/Quadruple Byte Program Command
(FWH Mode). The Double/Quadruple Byte Pro-
gram Command can be used to program two/four
adjacent Bytes to the memory array at a time. The
two Bytes must differ only for address A0; the four
Bytes must differ only for addresses A0 and A1.
Two Bus Write operations are required to issue the
command. The second Bus Write cycle latches the
start address and two/four data Bytes and starts
the Program/Erase Controller. Once the command
is issued, subsequent Bus Read operations read
Figure
Figure
Table
22., for a suggested flowchart on using
24., for a suggested flowchart on using
18..
PP
is not at V
Table
PPH
.
the contents of the Status Register. (See the sec-
tion on the Status Register for details on the defi-
nitions of the Status Register bits.)
During the Double/Quadruple Byte Program oper-
ation the memory will only accept the Read Status
register and Program/Erase Suspend commands.
All other commands are ignored.
Note that the Double/Quadruple Byte Program
command cannot change a bit set to ‘0’ back to ‘1’
and attempting to do so will not modify its value.
One of the erase commands must be used to set
all of the bits in the block to ‘1’.
See
the Double/Quadruple Byte Program command.
Typical Double/Quadruple Byte Program times
are given in
Chip Erase Command. The Chip Erase Com-
mand erases the entire memory array, setting all
of the bits to ‘1’. All previous data in the memory
array are lost. This command, though, is only
available under the A/A Mux interface.
Two Bus Write operations are required to issue the
command, and to start the Program/Erase Con-
troller. Once the command is issued, subsequent
Bus Read operations read the contents of the Sta-
tus Register. (See the section on the Status Reg-
ister for details on the definitions of the Status
Register bits.)
Erasing should not be attempted when V
at V
During the Chip Erase operation, the memory will
only accept the Read Status Register command.
All other commands are ignored.
See
the Chip Erase command. Typical Chip Erase
times are given in
Block Erase Command. The Block Erase com-
mand is used to erase a block, setting all of the bits
to ‘1’. All previous data in the block are lost.
Two Bus Write operations are required to issue the
command. The second Bus Write cycle latches the
block address and starts the Program/Erase Con-
troller. Once the command is issued, subsequent
Bus Read operations read the contents of the Sta-
tus Register. (See the section on the Status Reg-
ister for details on the definitions of the Status
Register bits.)
If the block is protected (FWH/LPC only) then the
Block Erase operation will abort, the data in the
block will not be changed, and the Status Register
will indicate the error.
During the Block Erase operation the memory will
only accept the Read Status Register and Pro-
gram/Erase Suspend commands. All other com-
mands are ignored.
PPH
Figure
Figure
, otherwise the result is uncertain.
23., for a suggested flowchart on using
26., for a suggested flowchart on using
Table
M50FLW040A, M50FLW040B
Table
18..
18..
PP
is not
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