FAN6921ML Fairchild Semiconductor, FAN6921ML Datasheet - Page 3

• Manufacturer Part Number: FAN6921ML
• Description: The highly integrated FAN6921ML combines a Power Factor Correction (PFC) controller and a Quasi-Resonant PWM controller
• Manufacturer: Fairchild Semiconductor

© 2010 Fairchild Semiconductor Corporation
FAN6921ML • Rev. 1.0.2
Internal Block Diagram
CSPWM
CSPFC
INV
DET
FB
10
11
5
3
4
2.65V
2.75V
Blanking
(4µs)
RANGE
2.3V
t
OFF
GND
5V
Blanking
Soft-Start
Compensation
9
Circuit
Over Power
9.5ms
2.5V
(8us/37µs/2.5ms)
Multi-Vector Amp.
I
Blanking
DET
Circuit
t
OFF-MIN
S/H
Internal
OTP
COMP
0.6V
V
2.5V
4.2V
I
DET
0.3V
2
2R
DET
Current Limit
R
2.75V
2.9V
V
DET OVP
PWM
CTL-PFC-ON/OFF
I
DET
Latched
RANGE
Figure 2. Functional Block Diagram
0.45V
Current Limit
Optimizer
PFC
100uA
THD
Detector
Latched
Valley
I
RT
OVP
UVP
2.5ms
32.5µs
12
RT
HV
16
1
0.8V
0.5V
st
I
HV
Starter
Valley
Timer
50ms
550ms / 150µs
/ Externally Triggering
Debounce
Debounce
70µs
27.5V
Prog. OTP
V
t
B
OFF-MIN
+9µs
Debounce
Latched
Time
3
OVP
Brownout
Latched
/t
Generator
Sawtooth
FB OLP
V
ON-MAX-PFC
V
100us
10ms
C
C
Multi Vector Amp.
0.8V
& PFC ON/OFF &
Latched
ON/OFF
V
18V/10V/7.5V
INV
Protection
1V/1.2V
Two Steps
Brownout
VDD
UVLO
1.2V
V
VIN
13
7
INV
Function
Disable
Output Over Power/ Overload (FB Pin)
Latched
(RT Pin) Externally Triggering
comparator
0.2V
Brownout
Output Open-Loop (FB Pin)
Output Short Circuit (FB
2.35V/2.15V
0.7V
S
R
Restarter
Inhibit
Timer
(RT Pin) Prog. OTP
SET
CLR
Startup
Pin)
Q
Q
VDD pin OVP
S
R
DET pin OVP
Internal OTP
SET
CLR
Debounce
100ms
PFC RANGE Control
Q
Q
V
V
COMP
I
B
ZCD
& clamp
to 1.6V
PFC Zero Current
Internal
Bias
DRV
Debounce
DRV
Detector
100ms
15.5V
17.5V
Protection
2.1V/1.75V
Lathed
10V
15
14
6
8
1
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RANGE
ZCD
OPFC
NC
OPWM