FAN6921ML Fairchild Semiconductor, FAN6921ML Datasheet - Page 19

• Manufacturer Part Number: FAN6921ML
• Description: The highly integrated FAN6921ML combines a Power Factor Correction (PFC) controller and a Quasi-Resonant PWM controller
• Manufacturer: Fairchild Semiconductor

© 2010 Fairchild Semiconductor Corporation
FAN6921ML • Rev. 1.0.2
High / Low Line Over-Power Compensation (DET Pin)
Generally, when the power switch turns off, there is a
delay from gate signal falling edge to power switch off.
This delay is produced by an internal propagation delay
of the controller and the turn-off delay of the PWM
switch due to gate resistor and gate-source capacitor
C
delay time produces different maximum output power
under the same PWM current limit level. Higher input
voltage generates higher maximum output power since
applied voltage on primary winding is higher and causes
higher rising slope inductor current. It results in higher
peak inductor current at the same delay. Furthermore,
under the same output wattage, the peak switching
current at high line is lower than at low line. Therefore,
to make the maximum output power close at different
input voltages, the controller needs to regulate V
the CSPWM pin to control the PWM switch current.
Referring to Figure 41, during the on time of the PWM
switch, the input voltage is applied to primary winding
and the voltage across on auxiliary winding, V
proportional to primary winding voltage. As the input
voltage increases, the reflected voltage on auxiliary
winding V
DET pin voltage and flows out a current I
current, I
can depend on this current I
regulate the current limit level of the PWM switch to
perform high / low line over-power compensation.
Figure 40. Measured Waveform of Valley Detection
ISS
of PWM switch. At different AC input voltage, this
DET
AUX
, is in accordance with V
rises as well. FAN6921ML also clamps the
Figure 39. Valley Detection
DET
during PWM on time to
AUX
, FAN6921ML
DET
. Since the
LIMIT
AUX
, is
of
As the input voltage increases, the reflected voltage on
the auxiliary winding, V
the current I
a lower level.
The R
the DET pin. Engineers can adjust this R
get proper V
characteristic curve of I
CSPWM pin is shown in Figure 42.
where V
winding; and N
Leading-Edge Blanking (LEB)
When the PFC or PWM switches are turned on, a
voltage spike is induced on the current-sense resistor
due to the reciprocal effect by reverse recovery energy
of the output diode and C
prevent this spike, a leading-edge blanking time is built-
in and a small RC filter is recommended between the
CSPWM pin and GND (e.g. 100Ω, 470pF).
I
19
DET
Figure 41. Relationship between V
DET

Figure 42. I
IN


V
resistor is connected from auxiliary winding to
is input voltage; N
IN
DET
LIMIT

P
) and the controller regulates the V

N N
is turn number of primary winding.
voltage to fit power system needs. The
A
DET
Current vs. V
Characteristic Curve
P
AUX
DET



, becomes higher (as well as
current vs. V
OSS
R
A
DET
is turn number of auxiliary
of power MOSFET. To
LIMIT
AUX
LIMIT
Voltage
DET
www.fairchildsemi.com
and V
voltage on
resistor to
LIMIT
IN
(1)
to