FAN6921ML Fairchild Semiconductor, FAN6921ML Datasheet
FAN6921ML
Available stocks
Related parts for FAN6921ML
FAN6921ML Summary of contents
Page 1
... RT pin and external shutdown, V output OVP, and brownin/out for AC input voltage under-voltage protection (UVP). The FAN6921ML controller is available in a 16-pin small outline package (SOP). Operating Temperature Range -40°C to +105°C 16-Pin Small Outline Package (SOP) June 2011 ...
Page 2
... Application Diagram © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.2 Figure 1. Typical Application 2 www.fairchildsemi.com ...
Page 3
... CSPWM Over Power Compensation t OFF-MIN (8us/37µs/2.5ms) t OFF S/H Blanking (4µs) 10 DET I 5V DET Internal OTP 9 GND © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0 RANGE OVP I HV OVP 2.75V 2.9V 27.5V Latched UVP Debounce 70µs 0.45V Latched Brownout Sawtooth THD Generator ...
Page 4
... CSPFC protection. When the sensed voltage across the PFC current-sensing resistor reaches the internal threshold (0.6 typical), the PFC switch is turned off to activate cycle-by-cycle current limiting. © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.2 - Fairchild Logo Z - Plant Code X - Year Code (1 Digit for SOP, 2 Digits for DIP) ...
Page 5
... PFC switching. This can be realized with an external circuit if disabling the PFC stage is desired connection High-voltage startup. HV pin is connected to the AC line voltage through a resistor (100kΩ t ypical for providing a high-charging current to V © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.2 capacitor www.fairchildsemi.com ...
Page 6
... The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol T Operating Ambient Temperature A © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.2 Parameter (3) (3) Parameter 6 Min. Max. ...
Page 7
... Threshold for RANGE VIN V VIN-RANGE-L Comparator t Range-Enable/Disable Debounce Time RANGE Output Low Voltage of RANGE V RANGE-OL Pin t PFC Maximum On Time ON-MAX-PFC © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.2 ), unless otherwise specified. J Conditions 0.16V, DD DD-ON Gate Open V =15V, OPFC; DD OPWM=100KHz =2nF ...
Page 8
... PFC Current Sense Section Threshold Voltage for Peak V CSPFC Current Cycle-by-Cycle Limit t Propagation Delay PD t Leading-Edge Blanking Time BNK A CSPFC Compensation Ratio for THD V © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.2 (Continued) ), unless otherwise specified. J Conditions (4) RANGE=Open RANGE=Ground INVH REF RANGE=Open V ...
Page 9
... Zero Duty-Cycle Input Voltage OZ V Open-Loop Protection Threshold Voltage FB-OLP t The Debounce Time for Open-Loop Protection FB-OLP t Internal Soft-Start Time FB-SS © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.2 (Continued) ), unless otherwise specified. J Conditions V = 25V DD V =15V, I =100mA =15V, I =100mA ...
Page 10
... PFC OFF Debounce Time to t PFC-OFF Disable PFC t Inhibit Time During t INHIB-PFC-OFF PFC ON Debounce Time to t (4) PFC-ON Enable PFC t Start Timer (Time-Out Timer) STARTER-PWM © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.2 (Continued) ), unless otherwise specified. J Conditions (4) V =0V DET I =-1mA DET I =1mA DET (4) ...
Page 11
... Threshold Voltage for Two-level V RT-OTP-LEVEL Debounce Time t Debounce Time for OTP RT-OTP-H Debounce Time for Externally t RT-OTP-L Triggering Note: 4. Guaranteed by design. © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.2 (Continued) ), unless otherwise specified. J Conditions V = 25V 15V, Io=100mA 15V, Io=100mA DD C ...
Page 12
... Temperature( ° C) Figure 9. Startup Current 2.60 2.55 2.50 2.45 2.40 -40 -25 - Temperature( ° C) Figure 11. PFC Output Feedback Reference Voltage © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.2 =25° 110 125 110 125 Figure 110 125 50 ...
Page 13
... Temperature( ° C) Figure 17. Beginning of Green-On Mode at V 9.0 8.5 8.0 7.5 7.0 -40 -25 - Temperature( ° C) Figure 19. PWM Minimum Off Time for V © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.2 (Continued) =25° 110 125 Figure 14. PFC Peak Current Limit Voltage 110 125 50 ...
Page 14
... Figure 21. Lower Clamp Voltage of DET Pin 110.0 105.0 100.0 95.0 90.0 -40 -25 - Temperature( ° C) Figure 23. Internal Source Current of RT Pin © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.2 (Continued) =25° 110 125 110 125 Figure 24. Over-Temperature Protection Threshold 14 2 ...
Page 15
... Multi-Vector Error Amplifier and THD Optimizer For better dynamic performance, faster transient response, and precise clamping on PFC output, FAN6921ML uses a transconductance type amplifier with proprietary innovative multi-vector error amplifier. The schematic diagram of this amplifier is shown in Figure 25. The PFC output voltage is detected from the ...
Page 16
... Figure 31. Operation Waveforms of PFC Protection for PFC Stage PFC Output Voltage UVP and OVP (INV Pin) FAN6921ML provides several kinds of protection for the PFC stage. PFC output over- and under-voltage are essential for PFC stage. Both are detected and determined by INV pin voltage, as shown in Figure 32. ...
Page 17
... COMP voltage results in narrow PFC on time, so that the energy converged is limited and the PFC output voltage decreases. When INV pin voltage is lower than 1.2V, FAN6921ML stops all PFC and PWM switching operation immediately until V voltage drops to turn-off voltage then rises to turn-on voltage again (UVLO) ...
Page 18
... V also decreases since auxiliary winding is coupled to primary winding. Once the V falls to negative, V (refer to Figure 39) and FAN6921ML is forced to flow out a current I this I threshold current, PWM gate signal is sent out after a fixed delay time (200ns typical). ...
Page 19
... V proportional to primary winding voltage. As the input voltage increases, the reflected voltage on auxiliary winding V rises as well. FAN6921ML also clamps the AUX DET pin voltage and flows out a current I current accordance with V ...
Page 20
... PWM transformer inductor; the voltage across on auxiliary winding is reflected from secondary winding and therefore the flat voltage on the DET pin is proportional to the output voltage. FAN6921ML can sample this flat voltage level after a t perform output over-voltage protection. This t blanking time is used to ignore the voltage ringing from leakage inductance of PWM transformer ...
Page 21
... Open-Loop, Short-Circuit, and Overload Protection (FB Pin) Referring to Figure 45, outside of FAN6921ML; the FB pin is connected to the collector of transistor of an opto- coupler. Inside of FAN6921ML, the FB pin is connected to an internal voltage bias through a resistor of ~5k. As the output loading is increased, the output voltage is decreased and the sink current of transistor of opto- coupler on primary side is reduced ...
Page 22
... Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.2 Figure 46. 16-Pin Small Outline Package (SOIC) 22 www.fairchildsemi.com ...
Page 23
... Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.2 23 www.fairchildsemi.com ...