FAN6920MR Fairchild Semiconductor, FAN6920MR Datasheet - Page 20

• Manufacturer Part Number: FAN6920MR
• Description: The highly integrated FAN6920MR combines Power Factor Correction (PFC) controller and quasi-resonant PWM controller
• Manufacturer: Fairchild Semiconductor

© 2010 Fairchild Semiconductor Corporation
FAN6920MR • Rev. 1.0.5
Green-Mode Operation and PFC-ON / OFF Control
(FB Pin)
Green mode further reduces power loss in the system
(e.g. switching loss). Through off-time modulation to
regulate switching frequency according to FB pin
voltage. When output loading decreases, FB voltage
lowers due to secondary feedback movement and the
t
voltage), the internal valley-detection circuit is activated
to detect the valley on the drain voltage of the PWM
switch. When the valley signal is detected, FAN6920MR
outputs a PWM gate signal to turn on the switch and
begin a new switching cycle.
With green mode operation and valley detection, at
light-load condition; the power system can perform
extended valley switching a DCM operation and can
further reduce switching loss for better conversion
efficiency. The FB pin voltage versus t
characteristic curve is shown in Figure 40. As Figure 40
shows, FAN6920MR can narrow down to 2.25ms t
time, which is around 440Hz switching frequency.
Referring to Figure 1 and Figure 2, FB pin voltage is not
only used to receive secondary feedback signal to
determine gate on-time, but also determines PFC stage
operating mode.
Valley Detection (DET Pin)
When FAN6920MR operates in green mode, t
determined by the green-mode circuit according to FB
pin voltage level. After t
detection circuit is activated. During t
switch, when transformer inductor current discharges to
zero, the transformer inductor and parasitic capacitor of
OFF-MIN
V
V
V
Figure 39. Typical Waveform of V
DD-OFF
DD-PWM-OFF
DD-ON
Gate
Figure 40. V
is extended. After t
Gate Signal at Hiccup Mode Operation
FB
Characteristic Curve
I
Voltage vs. t
DD-PWM-OFF
I
DD-OP
OFF-MIN
OFF-MIN
, the internal valley-
I
DD-ST
(determined by FB
OFF-MIN
DD
OFF
Voltage and
Time
of the PWM
OFF-MIN
OFF-MIN
time
OFF
is
PWM switch start to resonate concurrently. When the
drain voltage on the PWM switch falls, the voltage
across on auxiliary winding V
auxiliary winding is coupled to primary winding. Once
the V
voltage is clamped by the DET pin (refer to Figure 41)
and FAN6920MR is forced to flow out a current I
FAN6920MR reflects and compares this I
this source current rises to a threshold current, PWM
gate signal is sent out after a fixed delay time (200ns
typical).
High / Low Line Over-Power Compensation (DET Pin)
Generally, when the power switch turns off, there is a
delay from gate signal falling edge to power switch off.
This delay is produced by an internal propagation delay
of the controller and the turn-off delay of the PWM
switch due to gate resistor and gate-source capacitor
C
different maximum output power with the same PWM
current limit level. Higher input voltage generates higher
maximum output power because applied voltage on
primary winding is higher and causes higher rising slope
inductor current. It results in higher peak inductor
current at the same delay. Furthermore, under the same
output wattage, the peak switching current at high line is
lower than that at low line. Therefore, to make the
maximum output power close at different input voltages,
the controller needs to regulate V
CSPWM pin to control the PWM switch current.
Referring to Figure 1, during t
input voltage is applied to primary winding and the
voltage across on auxiliary winding V
to primary winding voltage. As the input voltage
increases, the reflected voltage on auxiliary winding
V
Figure 42. Measured Waveform of Valley Detection
20
AUX
ISS
. At different AC input voltages, this delay produces
becomes higher as well. FAN6920MR also clamps
AUX
OPWM
0V
0V
V
V
AUX
DET
voltage resonates and falls to negative, V
t
OFF
Figure 41. Valley Detection
detect valley
Start to
ON
AUX
of the PWM switch, the
also decreases since
from DET pin
I
det
LIMIT
flow out
AUX
Delay time and
then trigger
gate signal
voltage of the
is proportional
DET
switching
Valley
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current. If
DET
DET
.