FAN6920MR Fairchild Semiconductor, FAN6920MR Datasheet
FAN6920MR
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FAN6920MR Summary of contents
Page 1
... RT pin; and external NTC resistor, internal over-temperature shutdown, V pin OVP, and the DET pin over-voltage for output OVP, and brown-in / out for AC input voltage UVP. The FAN6920MR controller is available in a 16-pin small-outline package (SOP). Operating Temperature Range -40°C to +105°C ...
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... Application Diagram © 2010 Fairchild Semiconductor Corporation FAN6920MR • Rev. 1.0.5 Figure 1. Typical Application Circuit 2 www.fairchildsemi.com ...
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... Blanking Circuit 5 CSPWM Over-Power Compensation t OFF-MIN (5µs/20.5µs/2.25ms) t OFF S/H Blanking (2.5µs) 10 DET I 5V DET Internal OTP 9 GND © 2010 Fairchild Semiconductor Corporation FAN6920MR • Rev. 1.0 RANGE OVP I HV OVP 2.75V 2.9V 27.5V Auto-Recovery UVP Debounce 70µs V 0.45V COMP-H V COMP-L I COMP-BURST COMP-L ...
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... INV divider and provides PFC output over- and under-voltage protections. This pin also controls the PWM startup. Once the FAN6920MR is turned on and V Input to the PFC over-current protection comparator that provides cycle-by-cycle current limiting protection. When the sensed voltage across the PFC current-sensing resistor reaches the internal ...
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... PFC switching. This can be realized with an external circuit if disabling the PFC stage is desired connection High-voltage startup pin is connected to the AC line voltage through a resistor (100kΩ typical) for 16 HV providing a high charging current to V © 2010 Fairchild Semiconductor Corporation FAN6920MR • Rev. 1.0.5 Description capacitor www.fairchildsemi.com ...
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... The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol T Operating Ambient Temperature A © 2010 Fairchild Semiconductor Corporation FAN6920MR • Rev. 1.0.5 Parameter (3) (3) Parameter 6 Min. Max. ...
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... Range-Enable / Disable Debounce t RANGE Time V Output Low Voltage of RANGE Pin I RANGE-OL Output High Leakage Current of I RANGE-OH RANGE Pin t PFC Maximum On Time ON-MAX-PFC © 2010 Fairchild Semiconductor Corporation FAN6920MR • Rev. 1.0 unless otherwise specified. J Conditions 0.16V, DD DD-ON Gate Open V = 15V, DD OPFC, OPWM = 100kHz, ...
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... Comparator Output Low Voltage at V COMP-L PFC Burst Mode Zero Duty Cycle Voltage on COMP V OZ Pin Comparator Output Source Current I COMP Comparator Output Sink Current © 2010 Fairchild Semiconductor Corporation FAN6920MR • Rev. 1.0.5 (Continued unless otherwise specified. J Conditions (4) RANGE = Open RANGE = Ground INV-H ...
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... RESTART-PFC Inhibit Time (Maximum Switching t INHIB Frequency Limit) PFC Enable / Disable Function V ZCD-DIS Threshold Voltage PFC Enable / Disable Function t ZCD-DIS Debounce Time © 2010 Fairchild Semiconductor Corporation FAN6920MR • Rev. 1.0.5 (Continued unless otherwise specified. J Conditions COMP V = 25V 15V 100mA ...
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... Beginning of Green-On Mode Voltage Level Beginning of Green-Off Mode Voltage Level Hysteresis for Beginning of ∆V Green-Off Mode at FB Voltage G (4) Level © 2010 Fairchild Semiconductor Corporation FAN6920MR • Rev. 1.0.5 (Continued unless otherwise specified. J Conditions = V A / < V < 0.9 ...
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... Leading-Edge Blanking Time ON-BNK CSPWM Pin Floating V V CS-FLOATING Clamped High Voltage t Delay Time, CS Pin Floating CS-H © 2010 Fairchild Semiconductor Corporation FAN6920MR • Rev. 1.0.5 (Continued) ), unless otherwise specified. J Conditions RANGE Pin Internally Open RANGE Pin Internally Ground PFC Normal Operating Burst Mode PFC Burst Mode ...
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... Threshold Voltage for Two-Level V RT-OTP-LEVEL Debounce Time t Debounce Time for OTP RT-OTP-H Debounce Time for Externally t RT-OTP-L Triggering Note: 4. Guaranteed by design. © 2010 Fairchild Semiconductor Corporation FAN6920MR • Rev. 1.0.5 (Continued) ), unless otherwise specified. J Conditions V < RT-OTP-LEVEL 12 Min. Typ. Max. Units 125 ...
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... Figure 7. Turn-Off Threshold Voltage 16.0 14.0 12.0 10.0 8.0 6.0 -40 -25 - Temperature( Figure 9. Startup Current 2.60 2.55 2.50 2.45 2.40 -40 -25 - Temperature( Figure 11. PFC Output Feedback Reference Voltage © 2010 Fairchild Semiconductor Corporation FAN6920MR • Rev. 1.0.5 =25°C. A 7.85 7.75 7.65 7.55 7. 100 125 100 125 Figure 110 125 o C) ...
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... Temperature( Figure 17. Beginning of Green-On Mode 4.9 4.8 4.7 4.6 4.5 4.4 4.3 4.2 -40 -30 - Temperature (ºC) Figure 19. PWM Minimum Off-Time for V © 2010 Fairchild Semiconductor Corporation FAN6920MR • Rev. 1.0.5 (Continued) =25° 110 125 o C) Figure 14. PFC Peak Current Limit Voltage ...
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... Figure 21. Lower Clamp Voltage of DET Pin 110 105 100 95 90 -40 -25 - Temperature( Figure 23. Internal Source Current of RT Pin © 2010 Fairchild Semiconductor Corporation FAN6920MR • Rev. 1.0.5 (Continued) =25° 100 125 Figure 22. Reference Voltage for Output 110 125 ...
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... Multi-Vector Error Amplifier and THD Optimizer For better dynamic performance, faster transient response, and precise clamping on the PFC output, FAN6920MR uses a transconductance type amplifier with proprietary innovative multi-vector error amplifier. The schematic diagram of this amplifier is shown in Figure 25. The PFC output voltage is detected from the ...
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... Zero-Current Detection Protection for PFC Stage PFC Output Voltage UVP and OVP (INV Pin) FAN6920MR provides several kinds of protection for PFC stage. PFC output over- and under-voltage are essential for PFC stage. Both are detected and determined by INV pin voltage, as shown in Figure 32. ...
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... CSPFC OPFC Figure 33. Cycle-by-Cycle Current Limiting Brownout / In Protection (VIN Pin) With AC voltage detection, FAN6920MR can perform brownout / in protection (AC voltage UVP). Figure 34 shows the key operation waveforms of brownout / in protection. Both use the VIN pin to detect AC input voltage level and the VIN pin is connected to AC input by a resistor divider (refer to Figure 1) ...
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... The HV pin is connected to the AC line through a resistor (refer to Figure 1). With a built-in high-voltage startup circuit, when AC voltage is applied to the power system, FAN6920MR provides a high current to charge the external V startup time and build up normal rated output voltage within three seconds. To save power consumption, after ...
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... V auxiliary winding is coupled to primary winding. Once the V AUX voltage is clamped by the DET pin (refer to Figure 41) and FAN6920MR is forced to flow out a current I FAN6920MR reflects and compares this I I DD-ST this source current rises to a threshold current, PWM gate signal is sent out after a fixed delay time (200ns typical) ...
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... DET pin voltage and flows out current I current accordance with V DET FAN6920MR depends on this current during t regulate the current limit level of the PWM switch to perform high / low line over-power compensation. As the input voltage increases, the reflected voltage on the auxiliary winding V ...
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... Pin) blanking time is used Figure 47. FB Pin Open-Loop, Short Circuit, and R . The A DET Referring to Figure 47; outside of FAN6920MR, the FB pin is connected to the collector of transistor of an opto- coupler. Inside, the FB pin is connected to an internal (2) voltage bias through a resistor of around 5k the output loading is increased, the output voltage is decreased and the sink current of the transistor of the opto-coupler on primary side is reduced ...
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... Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/, © 2010 Fairchild Semiconductor Corporation FAN6920MR • Rev. 1.0.5 Figure 48. 16-Pin Small Outline Package (SOIC) 23 www.fairchildsemi.com ...
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... Fairchild Semiconductor Corporation FAN6920MR • Rev. 1.0.5 24 www.fairchildsemi.com ...