TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 60

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TMPM382FSFG

Manufacturer Part Number
TMPM382FSFG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMPM382FSFG

Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
64K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
64
Package
QFP(14x14)
Vcc
5V
Cpu Mhz
40
Ssp (ch) Spi
1
I2c/sio (ch)
1
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
N
Cs/wait Controller (ch)
-
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
-
12-bit Ad Converter
10
16-bit Timer / Counter
6
Motor / Igbt Control
Y
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
Y
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
-
Comparators
-
Low-voltage Detector
Y
Etm Hardware Trace
2-bit
7.1.2.2 Exception Handling and Branch to the Interrupt Service Routine (Pre-emption)
in the following order:
state of the stack after the register contents have been pushed.
fetch an ISR.
table is located at address 0x0000_0000 in the code space. By setting the Vector Table Offset Register,
it is possible to place the vector table at any address in the code or SRAM space.
When an exception occurs, the CPU suspends the currently executing process and branches to the
interrupt service routine. This is called “pre-emption”.
When the CPU detects an exception, it pushes the contents of the following eight registers to the stack
The SP is decremented by eight words by the completion of the stack push. The following shows the
At the same time as pushing the register contents to the stack, the CPU executes an instruction to
(1) Stacking
(2) Fetching an ISR
Prepare a vector table containing the top addresses of ISRs for each exception. After reset, the vector
The vector table should also contain the initial value of the main stack.
・Program Counter (PC)
・ Program Status Register (xPSR)
・ r0 - r3
・ r12
・ Link Register (LR)
Old SP
SP
TMPM380/M382 - 5 / 59 -
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xPSR
r12
PC
LR
r3
r2
r1
r0
TMPM380/M382

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