TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 363

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

13 Serial channel (UART/SIO)
13.3.8 Receive FIFO Operation
Receive FIFO
Receive shift register
Receive buffer
Receive interrupt (INTRX0)
SC0MOD2<RBFLL>
SC0MOD0<RXE>
the receive buffer full flag is cleared immediately. An interrupt will be generated according to
the SCxRFC<RIL> setting.
Note: When the data with parity bit are received in UART mode by using the FIFO, the parity
The following example describes the case a 4-byte data stream is received in the half duplex
mode:
SCxMOD1<6:5>=01 : Transfer mode is set to half duplex mode
SC0FCNF <4:0>=10111: Automatically inhibits continued reception after reaching the fill level.
SC0RFC<1:0>=00: The fill level of FIFO in which generated receive interrupt is set to 4-byte..
SC0RFC<7:6>=11: Clears receive FIFO and sets the condition of interrupt generation.
In this condition, 4-byte data reception may be initiated by setting the half duplex transmission
mode and writing “1” to the RXE bit. After receiving 4 bytes, the RXE bit is automatically
cleared and the receive operation is stopped (SCLK is stopped).
When FIFO is enabled, the received data is moved from receive buffer to receive FIFO and
I/O interface mode with SCLK output:
error flag is shown the occurring the parity error in the received data.
Second stage
Third stage
Forth stage
First stage
Fig 13-3 Receive FIFO Operation (1)
DATA1
The number of bytes to be used in the receive FIFO is the same as
the interrupt generation fill level.
TMPM380/M382 - 14 / 52 -
DATA2
DATA1
DATA1
DATA3
DATA2
DATA1
DATA2
DATA4
DATA3
DATA3
DATA1
DATA2
TMPM380/M382
DATA4
DATA3
DATA1
DATA4
DATA2