TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 369

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

13 Serial channel (UART/SIO)
13.3.13 Transmit FIFO Operation
FIFO. Once transmission is enabled, data is transferred to the transmit shift register from the
transmit buffer and start transmission. If data exists in the FIFO, the data is moved to the
transmit buffer immediately, and the <TBEMP> flag is cleared to "0".
Note: To use TX FIFO buffer, TX FIFO must be cleared after setting the SIO transfer mode (half
duplex/full duplex) and enabling FIFO (SCxFCNF<CNFG> = "1").
When FIFO is enabled, the maximum 5-byte data can be stored using the transmit buffer and
Transmit FIFO Forth stage
I/O interface mode with SCLK output (normal mode):
SC0MOD0<TXE>
Transmit interrupt (INTTX0)
Transmit shift register
SC0MOD2<TBEMP>
Transmit buffer
The following example describes the case a 4-byte data stream is transmitted:
SCxMOD1<6:5> 10 : Transfer mode is set to half duplex.
SCxFCNF<4:0> 01011 : Transmission is automatically disabled if FIFO becomes empty.
SCxTFC<1:0> 00 : Sets the interrupt generation fill level to "0".
SCxTFC<7:6> 11 : Clears receive FIFO and sets the condition of interrupt generation.
In this condition, data transmission can be initiated by setting the transfer mode to half
duplex, writing 5 bytes of data to the transmit FIFO, and setting the SC0MOD1<TXE> bit
to “1.” When the last transmit data is moved to the transmit buffer, the transmit FIFO
interrupt is generated. When transmission of the last data is completed, the clock is
stopped and the transmission sequence is terminated.
Second stage
Third stage
First stage
Fig 13-8 Transmit FIFO Operation(1)
TMPM380/M382 - 20 / 52 -
DATA4
DATA5
DATA3
DATA2
DATA1
The number of bytes to be used in the receive FIFO is the same
as the interrupt generation fill level.
DATA2
DATA5
DATA3
DATA4
DATA1
DATA5
DATA4
DATA3
DATA2
DATA5
DATA4
DATA3
TMPM380/M382
DATA5
DATA4
DATA5