TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 173

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

TBnEN
(0x4001_0xx0)
＜TBEN＞: Specifies the TMRBn operation. When the operation is disabled, no clock is supplied to the other
＜TBHALT＞: Specifies the control in HALT mode during debug mode.
9.4.1.1 TMRBn enable register (channels 0 through 7)
Read/Write
Read/Write
Read/Write
bit Symbol
Read/Write
After reset
bit Symbol
After reset
bit Symbol
After reset
bit Symbol
After reset
Function
registers in the TMRBn module. This can reduce power consumption. (This disables reading
from and writing to the other registers.)
To use the TMRBn, enable the TMRBn operation (set to “1”) before programming each register
in the TMRBn module.
After the TMRBn operation is executed and then disabled, the settings will be maintained in
each registers.
0: Clock not stops in HALT mode
1: Clock stops in HALT mode
operation
Disabled
Enabled
TMRBn
TBEN
R/W
31
23
15
R
R
R
0:
1:
7
0
0
0
0
Control in
TBHALT
Disabled
mode at
Enabled
debug
HALT
R/W
30
22
14
R
R
R
1:
6
0
0
0
0
0:
TMRBn enable register (n=0~7)
TMPM380/M382 - 7 / 34 -
29
21
13
R
R
R
5
0
0
0
28
20
12
R
R
R
4
0
0
0
27
19
11
R
R
R
3
0
0
0
“0” is read.
R
0
26
18
10
R
R
R
2
0
0
0
25
17
R
R
9
R
1
0
0
0
TMPM380/M382
24
16
R
R
8
R
0
0
0
0