73S1209F Maxim, 73S1209F Datasheet - Page 80

• Manufacturer Part Number: 73S1209F
• Description: The 73S1209F is a self-contained, SoC smart card reader IC that is an ideal solution for serially connected ISO 7816 design
• Manufacturer: Maxim

Smart Card Interrupt Register (SCInt): 0xFE01
When the smart card interrupt is asserted, the firmware can read this register to determine the actual
cause of the interrupt. The bits are cleared when this register is read. Each interrupt can be disabled by
the Smart Card Interrupt Enable register. Error processing must be handled by the firmware. This
register relates to the interface that is active – see the
80
SCInt.7
SCInt.6
SCInt.5
SCInt.4
SCInt.3
SCInt.2
SCInt.1
SCInt.0
Bit
MSB
WAITTO CRDEVT VCCTMRI
VCCTMRI
CRDEVT
TXEVNT
TXSENT
WAITTO
Symbol
RXERR
RXDAV
TXERR
Wait Timeout – An ATR or card wait timeout has occurred. In sync mode,
this interrupt is asserted when the RLen counter (it advances on falling
edges of CLK/ETU) reaches the loaded (max) value. This bit is cleared
when the SCInt register is read. When running in Synchronous Clock Stop
Mode, this bit becomes RLenINT interrupt (set when the Rlen counter
reaches the terminal count).
Card Event – A card event is signaled via pin DETCARD either when the
Card was inserted or removed (read the
presence) or there was a fault condition in the interface circuitry. This bit is
functional even if the smart card logic clock is disabled and when the
PWRDN bit is set. This bit is cleared when the SCInt register is read.
VCC Timer – This bit is set when the VCCTMR times out. This bit is cleared
when the SCInt register is read.
Rx Data Available – Data was received from the smart card because the Rx
FIFO is not empty. In bypass mode, this interrupt is generated on a falling
edge of the smart card I/O line. After receiving this interrupt in bypass
mode, firmware should disable it until the firmware has received the entire
byte and is waiting for the next start delimiter. This bit is cleared when there
is no RX data available in the RX FIFO.
TX Event – Set whenever the TXEMTY or TXFULL bits are set in the
SRXCtl
TX Sent – Set whenever the ISO UART has successfully transmitted a byte
to the smart card. Also set when a CRC/LRC byte is sent in T=1 mode. Will
not be set in T=0 when a break is detected at the end of a byte (when break
detection is enabled). This bit is cleared when the SCInt register is read.
TX Error – An error was detected during the transmission of data to the
smart card as indicated by either BREAKD or TXUNDR bit being set in the
STXCtl
description. This bit is cleared when the
RX Error – An error was detected during the reception of data from the
smart card. Additional information can be found in the
interrupt will be asserted for RXOVRR, or RX Parity error events. This bit is
cleared when the
SFR. Additional information can be found in that register
SFR. This bit is cleared when the
Table 74: The SCInt Register
RXDAV
SRXCtl
0x00
TXEVT
register is read.
SCSel
register (above).
Function
TXSENT
CRDCtl
STXCtl
STXCtl
TXERR
register is read.
register to determine card
register is read.
SRXCtl
RXERR
register. This
LSB
Rev. 1.2