73S1209F Maxim, 73S1209F Datasheet - Page 100

• Manufacturer Part Number: 73S1209F
• Description: The 73S1209F is a self-contained, SoC smart card reader IC that is an ideal solution for serially connected ISO 7816 design
• Manufacturer: Maxim

MSB
ATR Timeout Registers (ATRLsB): 0xFE20
MSB
These registers (ATRLsB and ATRLsB) form the ATR timeout (ATRTO [15:0]) parameter. Time in ETU
between the leading edge of the first character and leading edge of the last character of the ATR
response. Timer is enabled when the RCVATR is set and starts when leading edge of the first start bit is
received and disabled when the RCVATR is cleared. An ATR timeout is generated if this time is
exceeded.
TS Timeout Register (STSTO): 0xFE21
The TS timeout is the time in ETU between the de-assertion of smart card reset and the leading edge of
the TS character in the ATR (when DETTS is set). The timer is started when smart card reset is
de-asserted. An ATR timeout is generated if this time is exceeded (MUTE card).
Reset Time Register (RLength): 0xFE22
Time in ETUs that the hardware delays the de-assertion of RST. If set to zero and RSTCRD = 0, the
hardware adds no extra delay and the hardware will release RST after VCCOK is asserted during
power-up. If set to one, it will delay the release of RST by the time in this register. When the firmware
sets the RSTCRD bit, the hardware will assert reset (RST = 0 on pin). When firmware clears the bit, the
hardware will release RST after the delay specified in Rlen. If firmware sets the RSTCRD bit prior to
instructing the power to be applied to the smart card, the hardware will not release RST after power-up
until RLen after the firmware clears the RSTCRD bit. This provides a means to power up the smart card
and hold it in reset until the firmware wants to release the RST to the selected smart card. Works with
the selected smart card interface.
100
ATRTO.15
ATRTO.7
MSB
MSB
TST0.7
RLen.7
ATRTO.14
ATRTO.6
TST0.6
RLen.6
ATRTO.13
ATRTO.5
TST0.5
RLen.5
Table 105: The ATRMsB Register
Table 104: The ATRLsB Register
Table 106: The STSTO Register
Table 107: The RLength Register
ATRTO.12 ATRTO.11 ATRTO.10 ATRTO.9 ATRTO.8
ATRTO.4
0x00
TST0.4
RLen.4
0x70
0x00, (ATRMsB): 0xFE1F
ATRTO.3
TST0.3
RLen.3
ATRTO.1
TST0.1
RLen.1
TST0.2
RLen.2
0x00
ATRTO.2 ATRTO.0
TST0.0
RLen.0
LSB
LSB
LSB
LSB
Rev. 1.2