73S1209F Maxim, 73S1209F Datasheet - Page 29

• Manufacturer Part Number: 73S1209F
• Description: The 73S1209F is a self-contained, SoC smart card reader IC that is an ideal solution for serially connected ISO 7816 design
• Manufacturer: Maxim

DS_1209F_004
External Interrupt Control Register (INT5Ctl): 0xFF94
Miscellaneous Control Register 0 (MISCtl0): 0xFFF1
Rev. 1.2
MISCtl0.7
MISCtl0.6
MISCtl0.5
MISCtl0.4
MISCtl0.3
MISCtl0.2
MISCtl0.1
MISCtl0.0
INT5Ctl.7
INT5Ctl.6
INT5Ctl.5
INT5Ctl.4
INT5Ctl.3
INT5Ctl.2
INT5Ctl.1
INT5Ctl.0
Bit
Bit
MSB
MSB
PWRDN
PDMUX
PWRDN
Symbol
SLPBK
SSEL
PDMUX
Symbol
KPIEN
KPINT
–
–
–
–
–
–
–
–
–
–
–
–
This bit sets the circuit into a low-power condition. All analog (high speed
oscillator and VCO/PLL) functions are disabled 32 MPU clock cycles after
this bit is set=1. This allows time for the next instruction to set the STOP bit
in the
mode. When set, this bit overrides the individual control bits that otherwise
control power consumption.
UART loop back testing mode.
Serial port pins select.
When set=1, enables interrupts from Keypad (normally going to int5),
Smart Card interrupts (normally going to int4), or USR(7:0) pins (int0) to
cause interrupt on int0. The assertion of the interrupt to int0 is delayed by
512 MPU clocks to allow the analog circuits, including the clock system, to
stabilize. This bit must be set prior to asserting the PWRDN bit in order to
properly configure the interrupts that will wake up the circuit. This bit is
reset=0 when this register is read.
Keypad interrupt enable.
Keypad interrupt flag.
PCON
–
–
Table 14: The INT5Ctl Register
Table 15: The MISCtl0 Register
register to stop the CPU core. The MPU is not operative in this
–
–
–
–
0x00
0x00
Function
Function
–
–
SLPBK
KPIEN
KPINT
SSEL
73S1209F Data Sheet
LSB
LSB
29