73S1209F Maxim, 73S1209F Datasheet - Page 32

• Manufacturer Part Number: 73S1209F
• Description: The 73S1209F is a self-contained, SoC smart card reader IC that is an ideal solution for serially connected ISO 7816 design
• Manufacturer: Maxim

corresponding flag can be individually enabled or disabled by the enable bits in SFRs IEN0, IEN1, and
IEN2. Some of the 10 sources are multiplexed in order to expand the number of interrupt sources.
1.7.3
The 80515 core provides 10 interrupt sources with four priority levels. Each source has its own request
flag(s) located in a special function register (TCON, IRCON, and SCON). Each interrupt requested by the
IEN2. Some of the 10 sources are multiplexed in order to expand the number of interrupt sources.
These will be described in more detail in the respective sections.
These will be described in more detail in the respective sections.
External interrupts are the interrupts external to the 80515 core, i.e. signals that originate in other parts of
External interrupts are the interrupts external to the 80515 core, i.e. signals that originate in other parts of
the 73S1209F, for example the USR I/O, smart card interface, analog comparators, etc. The external
the 73S1209F, for example the USR I/O, smart card interface, analog comparators, etc. The external
interrupt configuration is shown in Figure 8.
interrupt configuration is shown in Figure 8.
32
Interrupts
Card_Det
VCC_OK
USR2
USR5
USR6
USR0
USR1
USR3
USR4
USR7
KeyPad
Serial
Serial
INT3
Analog
Ch 0
Ch 1
INT2
Comp
I
2
VccCTL
CRDCtl
C
Figure 8: External Interrupt Configuration
Pads
Pads
USR
INT
+
VDD_Fault
Card Event
VCC_TMR
USR
USR
Int
Ctl
Wait Timeout
Ctl
USR
Int
USR
Ctl
Int
Ctl
Int
TX_Event
TX_Error
RX_Error
Tx_Sent
RxData
INT5
INT6
Ctl
Ctl
PDMUXCtl
SCInt
when PWRDN bit is set
During STOP, IDLE
+
SCIE
Delay
0
1
+
t0
int4
int5
int6
SerChan 0 int
SerChan 1 int
int0
int1
int2
int3
t1
Clear PWRDN bit
CORE
MPU
Rev. 1.2