73S1209F Maxim, 73S1209F Datasheet - Page 122

• Manufacturer Part Number: 73S1209F
• Description: The 73S1209F is a self-contained, SoC smart card reader IC that is an ideal solution for serially connected ISO 7816 design
• Manufacturer: Maxim

Revision History
122
Revision
1.0
1.1
1.2
Date
4/4/2007
11/7/2007
12/16/2008
Description
First publication.
In
In
and 32-cycle references.
In
must be bound between a value of 1 to 7. The possible crystal or external
clock are shown in Table 12.“ to “Mcount is configured in the MCLKCtl
register must be bound between a value of 1 to 7. The possible crystal or
external clock frequencies for getting MCLK = 96MHz are shown in Table
11.”
In the
using timer 1.” to “If BSEL = 0, the baud rate is derived using timer 1.”
In
description: “The signals of the emulator port have weak pull-ups. Adding
resistor footprints for signals E_RST, E_TCLK and E_RXTX on the PCB is
recommended. If necessary, adding 10KΩ pull-up resistors on E_TCLK
and E_RXTX and a 3KΩ on E_RST will help the emulator operate
normally if a problem arises.”
Added
In
In
VCC, VPC, SEC, TEST and VDD pins.
In
“FLSH_PGADR” to “PGADDR”. Added “The PGADDR register denotes
the page address for page erase. The page size is 512 (200h) bytes and
there are 128 pages within the flash memory. The PGADDR denotes the
upper seven bits of the flash memory address such that bit 7:1 of the
PGADDR corresponds to bit 15:9 of the flash memory address. Bit 0 of
the PGADDR is not used and is ignored.” In the description of the
PGADDR
(see detailed description above).”
In
In
In
detailed description above).” to the PGADDR description.
In
FUSECtl bit description to TRIMPCtl.
In
In
In
In
the activation sequence begins (either by VCCOK = 1 or VCCTMR
timeout) and will go high ½ the ETU period thereafter.”
In
SYCKST is set=1(STXCtl, b7=1), Rlen=max will stop the clock at the
selected (CLKLVL or SCLKLVL) level.”
In
Table
Section
Section
Section
Ordering
Table
Section
Table
Table
Table
Table
Table
Table
Table
Section
Section 1.7.13.5
Section
BRCON
Section 4, Equivalent
1, added the Type column and the Equivalent Circuit references.
1, added more description to the SCL, SDA, PRES, PRESB,
3, change “FLSH_PGADR” to “PGADDR”.
3, changed “FLSHCRL” to “FLSHCTL”.
3, added “Note: the page address is shifted left by one bit (see
5, moved the TRIMPCtl bit description to FUSECtl and moved the
6, changed “PGADR” to “PGADDR”.
7, added PGADDR.
11, removed the Mcount 7 row.
register, added “Note: the page address is shifted left by one bit
1.4, updated program security description to remove pre-boot
1.7.1, changed “Mcount is configured in the MCLKCtl register
1.7.12, removed the following from the emulator port
1.3.2, changed “FLSH_ERASE” to “ERASE” and
1.7.13.5, deleted “The ETU clock is held in reset condition until
1.7.13.5, deleted number 9.
Information, removed the leaded part numbers.
description, changed “If BSEL = 1, the baud rate is derived
(number 3), deleted “If CLKOFF/SCLKOFF is high and
Circuits.
Rev. 1.2