73S1209F Maxim, 73S1209F Datasheet - Page 49

• Manufacturer Part Number: 73S1209F
• Description: The 73S1209F is a self-contained, SoC smart card reader IC that is an ideal solution for serially connected ISO 7816 design
• Manufacturer: Maxim

DS_1209F_004
1.7.7
The 73S1209F includes 9 pins of general purpose digital I/O (GPIO). On reset or power-up, all USR pins
are inputs until they are configured for the desired direction. The pins are configured and controlled by
the USR and UDIR SFRs. Each pin declared as USR can be configured independently as an input or
output with the bits of the UDIRn registers. Table 48 lists the direction registers and configurability
associated with each group of USR pins. USR pins 0 to 7 are multiple use pins that can be used for
general purpose I/O, external interrupts and timer control.
Table 49 shows the configuration for a USR pin through its associated bit in its UDIR register. Values
read from and written into the GPIO ports use the data registers
USR pins are defaulted as inputs and pulled up to VDD until any write to the corresponding UDIR register
is performed. This insures all USR pins are set to a known value until set by the firmware. Unused USR
pins can be set for output if unused and unconnected to prevent them from floating. Alternatively, unused
USR pins can be set for input and tied to ground or V
Four XRAM SFR registers (USRIntCtl1, USRIntCtl2, USRIntCtl3, and USRIntCtl4) control the use of the
USR [7:0] pins. Each of the USR [7:0] pins can be configured as GPIO or individually be assigned an
internal resource such as an interrupt or a timer/counter control. Each of the four registers contains two
3-bit configuration words named UxIS (where x corresponds to the USR pin). The control resources
selectable for the USR pins are listed in Table 74 through Table 78. If more than one input is connected
to the same resource, the resources are combined using a logical OR.
Note: x denotes the corresponding USR pin. Interrupt edge or level control is assigned in the IT0 and IT1
bits in the
Rev. 1.2
User (USR) Ports
TCON
USR_0…USR_7
USR Pin Group
Table 48: Direction Registers and Internal Resources for DIO Pin Groups
USR_8
register.
UxIS Value
Table 50: Selectable Controls Using the UxIS Bits
0
1
2
3
4
5
6
7
GPIO only
USR Pin
Function
Multi-use
Type
Table 49: UDIR Control Bit
Resource Selected for USRx Pin
Interrupt 0 rising edge/high level on USRx
Interrupt 1 rising edge/high level on USRx
Interrupt 0 falling edge/low level on USRx
Interrupt 1 falling edge/low level on USRx
Direction
Register
UDIR70
UDIR8
Name
T0 (counter0 gate/clock)
T1 (counter1 gate/clock)
DD
output
.
0
None
None
Direction
0x91 [7:0]
UDIR Bit
Location
Register
0xA1 [0]
(SFR)
USR70
input
1
Register
and USR8. Note: After reset, all
USR70
Name
USR8
Data
73S1209F Data Sheet
0x90 [7:0]
Location
Register
0xA0 [0]
(SFR)
Data
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