73S1209F Maxim, 73S1209F Datasheet - Page 55
73S1209F
Manufacturer Part Number
73S1209F
Description
The 73S1209F is a self-contained, SoC smart card reader IC that is an ideal solution for serially connected ISO 7816 design
Manufacturer
Maxim
Datasheet
1.73S1209F.pdf
(123 pages)
- Current page: 55 of 123
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DS_1209F_004
Figure 9 shows the timing of the I
1.7.10.2 I
To read data on the I
in this sequence:
1. Write slave device address to Device Address register (DAR). The data contains 7 bits device
2. Write control data to Control and Status register (CSR). Write a 1 to bit 1 to start I
3. Wait for I
4. Read data from the Read Data register (RDR).
5. Read data from Secondary Read Data register (SRDR) if bit 0 of Control and Status register (CSR) is
Rev. 1.2
address and 1 bit of op-code. The op-code bit should be written with a 1.
Also write a 1 to bit 0 if the Secondary Read Data register (SRDR) is to be captured from the I
Slave device.
Refer to information about the INT6Ctl,
written with a 1.
Transfer length
Transfer length
I2C_Interrupt
I2C_Interrupt
(CSR bit1)
(CSR bit0)
(CSR bit1)
Start I2C
(CSR bit0)
Start I2C
2
SDA
SCL
C Read Sequence
SDA
SCL
2
C interrupt to be asserted. It indicates that the read operation on the I
2
C Master Bus from a slave device, the 80515 has to program the following registers
condition
condition
condition
START
START
START
MSB
MSB
Device Address
Device Address
2
Figure 9: I
C write mode.
C write mode.
1-7
1-7
1-7
[7:0]
[7:0]
LSB
IEN1
LSB
8
8
8
2
C Write Mode Operation
ACK bit
ACK bit
ACK bit
and
9
9
9
IRCON
MSB
MSB
Write Data [7:0
Write Data [7:0]
10-17
10-17
10-17
registers for masking and flag operation.
LSB
LSB
ACK bit
ACK bit
ACK bit
18
18
18
MSB
Secondary Write
condition
condition
STOP
STOP
Data [7:0]
19-26
LSB
73S1209F Data Sheet
2
ACK bit
C bus is done.
2
27
C Master Bus.
condition
STOP
2
C
55
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