71M6543F Maxim, 71M6543F Datasheet - Page 82

• Manufacturer Part Number: 71M6543F
• Description: The 71M6543F/71M6543H are Teridian's 4th-generation polyphase metering system-on-chips (SoCs) with a 5MHz, 8051-compatible MPU core, low-power real-time clock (RTC) with digital temperature compensation, flash memory, and LCD driver
• Manufacturer: Maxim

71M6543F/H and 71M6543G/GH Data Sheet
In normal operation, the WDT is reset by periodically writing a one to the WD_RST control bit I/O RAM
0x28B4[7]). The watchdog timer is also reset when the 71M6543 wakes from LCD or SLP mode, and
when ICE_E=1.
3.4
As described above, the part always wakes up in MSN mode when system power is restored. As stated
in
up timer timeout, when the pushbutton (PB) input is activated, a rising edge on SEGDIO4, SEGDIO52 or
SEGDIO55, or by activity on the RX or OPT_RX pins.
3.4.1 Wake on Hardware Events
The following pin signal events wake the 71M6543 from SLP or LCD mode: a high level on the PB pin, either
edge on the RX pin, a rising edge on the SEGDIO4 pin, a high level on the SEGDIO52 pin, or a high level on
the SEGDIO55 pin or either edge on the OPT_RX pin. See
for further details on the OPT_RX/SEGDIO55 pin. The SEGDIO4, SEGDIO52, and SEGDIO55 pins must
be configured as DIO inputs and their wake enable (EW_x bits) must be set. In SLP and LCD modes, the
MPU is held in reset and cannot poll pins or react to interrupts. When one of the hardware wake events
occurs, the internal WAKE signal rises and within three CK32 cycles the MPU begins to execute. The
MPU can determine which one of the pins awakened it by checking the WF_PB, WF_RX, WF_SEGDIO4,
WF_DIO52, or WF_DIO55 flags (see
If the part is in SLP or LCD mode, it can be awakened by a high level on the PB pin. This pin is normally
pulled to GND and can be connected externally so it may be pulled high by a push button depression.
Some pins are de-bounced to reject EMI noise. Detection hardware ignores all transitions after the initial
transition.
Pins that do not have de-bounce circuits must still be high for at least 2 µs to be recognized.
The wake enable and flag bits are shown in
MPU wakes from a wake event. Note that the PB flag is set whenever the PB is pushed, even if the part
is already awake.
In addition to push buttons and timers, the part can also reboot due to the RESET pin, the RESET bit (I/O
RAM 0x2200[3]), the WDT, the cold start detector, and E_RST. As seen in
mechanisms has a flag bit to alert the MPU to the source of the wakeup. If the wakeup is caused by
return of system power, there is no active WF flag and the VSTAT[2:0] field (SFR 0xF9[2:0]) indicates that
system power is stable.
82
WAKE_ARM
EW_DIO52
EW_DIO55
EW_DIO4
3.2 Battery Modes,
EW_PB
EW_RX
Name
Always Enabled
Always Enabled
Always Enabled
Wake Enable
Wake-Up Behavior
Table 64
Location
28B2[5]
28B3[3]
28B3[4]
28B3[2]
28B3[1]
28B3[0]
Table 66
shows which pins are equipped with de-bounce circuitry.
transitions from both LCD and SLP mode to BRN mode can be initiated by a wake-
lists the events that clear the WF flags.
© 2008–2011 Teridian Semiconductor Corporation
WF_RSTBIT
WF_DIO52
WF_DIO55
WF_DIO4
WF_ERST
WF_TMR
WF_RST
WF_PB
WF_RX
Name
Table 64: Wake Enable and Flag Bits
Wake Flag
Table
64).
Location
Table
28B1[5]
28B1[3]
28B1[4]
28B1[2]
28B1[1]
28B1[0]
28B0[6]
28B0[5]
28B0[3]
64. The wake flag bits are set by hardware when the
De-bounce
Table 64
2 µs
2 µs
Yes
2 µs
2 µs
Yes
Yes
No
No
for de-bounce details on each pin and
Description
Wake on Timer.
Wake on PB.*
Wake on either edge of RX.
Wake on SEGDIO4.
Wake on SEGDIO52.*
OPT_RXDIS = 1: Wake on DIO55 with
64 ms de-bounce.*
OPT_RXDIS = 0: Wake on either edge
of OPT_RX with 2 µs de-bounce.
OPT_RXDIS: I/O RAM 0x2457[2]
Wake after RESET.
Wake after RESET bit.
Wake after E_RST.
(ICE must be enabled)
Table
64, each of these
v1.2