71M6543F Maxim, 71M6543F Datasheet - Page 38

• Manufacturer Part Number: 71M6543F
• Description: The 71M6543F/71M6543H are Teridian's 4th-generation polyphase metering system-on-chips (SoCs) with a 5MHz, 8051-compatible MPU core, low-power real-time clock (RTC) with digital temperature compensation, flash memory, and LCD driver
• Manufacturer: Maxim

71M6543F/H and 71M6543G/GH Data Sheet
2.4.7 Timers and Counters
The 80515 has two 16-bit timer/counter registers: Timer 0 and Timer 1. These registers can be configured
for counter or timer operations.
In timer mode, the register is incremented every machine cycle, i.e. it counts up once for every 12 periods of
the MPU clock. In counter mode, the register is incremented when the falling edge is observed at the
corresponding input signal T0 or T1 (T0 and T1 are the timer gating inputs derived from certain DIO pins, see
2.5.10 Digital
is 1/2 of the clock frequency (CKMPU). There are no restrictions on the duty cycle, however to ensure proper
recognition of the 0 or 1 state, an input should be stable for at least 1 machine cycle.
Four operating modes can be selected for Timer 0 and Timer 1, as shown in
TMOD (SFR 0x89) register, shown in
Table
(SFR 0x88) register, which is shown in
register start their associated timers when set.
38
S0CON[3]
S0CON[2]
S0CON[1]
S0CON[0]
S1CON[7]
S1CON[5]
S1CON[4]
S1CON[3]
S1CON[2]
S1CON[1]
S1CON[0]
PCON[7]
Bit
Bit
Bit
24, is used to select the appropriate mode. The timer/counter operation is controlled by the TCON
I/O). Since it takes 2 machine cycles to recognize a 1-to-0 event, the maximum input count rate
TB80
RB80
TI0
RI0
SM
SM21
REN1
TB81
RB81
TI1
RI1
SMOD
Symbol
Symbol
Symbol
Table 20: The S1CON (UART1) Register (SFR 0x9B)
Table 21:
© 2008–2011 Teridian Semiconductor Corporation
The 9th transmitted data bit in Modes 2 and 3. Set or cleared by the MPU,
depending on the function it performs (parity check, multiprocessor
communication etc.)
In Modes 2 and 3 it is the 9
stop bit. In mode 0, this bit is not used. Must be cleared by software.
Transmit interrupt flag; set by hardware after completion of a serial transfer. Must
be cleared by software (see Caution above).
Receive interrupt flag; set by hardware after completion of a serial reception. Must
be cleared by software (see Caution above).
Sets the baud rate and mode for UART1.
Enables the inter-processor communication feature.
If set, enables serial reception. Cleared by software to disable reception.
The 9
on the function it performs (parity check, multiprocessor communication etc.)
In Modes A and B, it is the 9
the stop bit. Must be cleared by software
Transmit interrupt flag, set by hardware after completion of a serial transfer. Must
be cleared by software (see Caution above).
Receive interrupt flag, set by hardware after completion of a serial reception. Must
be cleared by software (see Caution above).
The SMOD bit doubles the baud rate when set
th
SM
PCON Register Bit Description (
0
1
Table
transmitted data bit in Mode A. Set or cleared by the MPU, depending
25. Bits TR1 (TCON[6]) and TR0 (TCON[4]) in the TCON
Mode
A
B
th
th
data bit received. In Mode 1, SM20 is 0, RB80 is the
Description
9-bit UART
8-bit UART
data bit received. In Mode B, if SM21 is 0, RB81 is
Function
Function
Function
SFR 0x87
Baud Rate
Table 22
variable
variable
)
and
Table
23. The
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