71M6543F Maxim, 71M6543F Datasheet - Page 55

• Manufacturer Part Number: 71M6543F
• Description: The 71M6543F/71M6543H are Teridian's 4th-generation polyphase metering system-on-chips (SoCs) with a 5MHz, 8051-compatible MPU core, low-power real-time clock (RTC) with digital temperature compensation, flash memory, and LCD driver
• Manufacturer: Maxim

For the 71M6543H and 71M6543GH in BRN mode (with TEMP_PWR=TEMP_BSEL):
2.5.5 71M6543 Temperature Sensor
The 71M6543 includes an on-chip temperature sensor for determining the temperature of its bandgap
reference. The primary use of the temperature data is to determine the magnitude of compensation
required to offset the thermal drift in the system for the compensation of current, voltage and energy
measurement and the RTC. See
RTC Temperature Compensation
Unlike earlier generation Teridian SoCs, the 71M6543 does not use the ADC to read the temperature
sensor. Instead, it uses a technique that is operational in SLP and LCD mode, as well as BRN and MSN
modes. This means that the temperature sensor can be used to compensate for the frequency variation
of the crystal, even in SLP mode while the MPU is halted. See
on page 53.
In MSN and BRN modes, the temperature sensor is awakened on command from the MPU by setting the
TEMP_START (I/O RAM 0x28B4[6]) control bit. In SLP and LCD modes, it is awakened at a regular rate
set by TEMP_PER[2:0] (I/O RAM 0x28A0[2:0]).
The result of the temperature measurement is read from the two I/O RAM locations STEMP[10:3] (I/O
RAM 0x2881) and STEMP[2:0] (I/O RAM 0x2882[7:5]). Note that both of these I/O RAM locations must be
read and properly combined to form the STEMP[10:0] 11-bit value (see STEMP in
11-bit value is in 2’s complement form and ranges from -1024 to +1023 (decimal).
The equations below are used to calculate the sensed temperature. The first equation applies when the
71M6543F and 71M6543G are in MSN mode and TEMP_PWR = 1. The second equation applies when the
71M6543F and 71M6543G are in BRN mode, and in this case, the TEMP_PWR and TEMP_BSEL bits must
both be set to the same value, so that the battery that supplies the temperature sensor is also the battery
that is measured and reported in BSENSE. Thus, the second equation requires reading STEMP and
BSENSE. In the second equation, BSENSE (the sensed battery voltage) is used to obtain a more accurate
temperature reading when the IC is in BRN mode. A second set of equations if provided for the
71M6543H and 71M6543GH high precision parts. The coefficients provided in the various STEMP
equations below are typical.
For the 71M6543F and 71M6543G in MSN Mode (with TEMP_PWR = 1):
For the 71M6543F and 71M6543G in BRN Mode, (with TEMP_PWR=TEMP_BSEL):
If STEMP ≤ 0:
If STEMP > 0:
v1.2
RTC_TMIN[5:0] 289E[5:0]
RTC_THR[4:0]
Name
Temp
�������� ( ℃ ) = 0.325 ∙ ���������� + 0.00218 ∙ ������������
�������� ( ℃ ) =
Location Rst
289F[4:0]
(
o
C
)
=
. 0
© 2008–2011 Teridian Semiconductor Corporation
Table 45: I/O RAM Registers for RTC Interrupts
325
63 ∙ ����������
��������_85
0
0
4.5 Metrology Temperature Compensation
⋅
STEMP
on page 53.
Wk
0
0
Temp
+ 0.00218 ∙ ������������
R/W The target minutes register. See below.
R/W
(
+
Dir
°
C
. 0
)
00218
=
The target hours register. The RTC_T interrupt occurs
when RTC_MIN[5:0] becomes equal to RTC_TMIN[5:0]
and RTC_HR[4:0] becomes equal to RTC_THR[4:0].
. 0
Description
325
⋅
⋅
STEMP
BSENSE
71M6543F/H and 71M6543G/GH Data Sheet
2
+
2.5.4.4 RTC Temperature Compensation
− 0.609 ∙ ������������ + 64.4
2
22
2
− 0.609 ∙ ������������ + 64.4
−
. 0
609
⋅
on page 89. Also see
BSENSE
Table
+
46). The resulting
64
4 .
2.5.4.4
55