71M6543F Maxim, 71M6543F Datasheet - Page 138

• Manufacturer Part Number: 71M6543F
• Description: The 71M6543F/71M6543H are Teridian's 4th-generation polyphase metering system-on-chips (SoCs) with a 5MHz, 8051-compatible MPU core, low-power real-time clock (RTC) with digital temperature compensation, flash memory, and LCD driver
• Manufacturer: Maxim

71M6543F/H and 71M6543G/GH Data Sheet
6.4.5 Supply Current
The supply currents provided in
Refer to the 71M6xxx Data Sheet for additional current required when using a 71M6x03 remote sensor.
Parameter
I1:
V3P3A + V3P3SYS current,
Normal Operation
I1a:
V3P3A + V3P3SYS current,
ADC Half Rate
(ADC_DIV=1)
I1b:
V3P3A + V3P3SYS current,
Normal Operation
PLL_FAST=0
I1c:
V3P3A + V3P3SYS current,
Normal Operation
PRE_E=1
I1d:
V3P3A + V3P3SYS current,
Normal Operation
PRE_E=1, ADC_DIV=1,
FIR_LEN=0.
(see note 1)
I1e:
V3P3A + V3P3SYS current,
Normal Operation
PLL_FAST=0, PRE_E=1.
(see note 1)
I2:
V3P3A + V3P3SYS dynamic
current
VBAT current
I3: MSN Mode
I4: BRN Mode
I5: LCD Mode (ext. VLCD)
I6: LCD Mode (boost, DAC)
I7: LCD Mode (DAC)
I8: LCD Mode (VBAT)
I9: SLP Mode
VBAT_RTC current
I10: MSN
I11: BRN
I12: LCD Mode
I13: SLP Mode
I14: SLP Mode (see note 1)
I15:
V3P3A + V3P3SYS current,
Write Flash with ICE
138
Notes:
1.
2.
3.
Guaranteed by design; not production tested.
LCD_DAC[4:0]=5 (2.9V), LCD_CLK[1:0]=2, LCD_MODE[2:0]=6, all LCD_MAPn bits = 0.
LCD_DAC[4:0]=5 (2.9V), LCD_CLK[1:0]=2, LCD_MODE[2:0]=6, LCD_BLANK=0, LCD_ON=1, all LCD_MAPn bits = 1 and VLCD pin = 3.3V.
Table 95: Supply Current Performance Specifications
Condition
Polyphase: 4 Currents, 3 Voltages
V3P3A = V3P3SYS = 3.3 V,
MPU_DIV [2:0]= 3 (614 kHz MPU clock),
No Flash memory write,
RTM_E=0, PRE_E=0, CE_E=1, ADC_E=1,
ADC_DIV=0, MUX_DIV[3:0]=7,
FIR_LEN[1:0]=1, PLL_FAST=1
Same as I1, except ADC_DIV=1, FIR_LEN=0
Same as I1, except PLL_FAST=0
Same as I1, except PRE_E=1
Same as I1, except PRE_E=1, ADC_DIV=1,
FIR_LEN=0.
Same as I1, except PRE_E=1, PLL_FAST=0.
Same as I1, except with variation of
MPU_DIV[2:0].
CE_E=0
LCD_VMODE[1:0]=3, also see note 3
LCD_VMODE[1:0]=2, also see notes 1, 2
LCD_VMODE[1:0]=1, also see notes 1, 2
LCD_VMODE[1:0]=0, also see notes 1, 2
SLP Mode
LCD_VMODE[1:0]=2, also see note 3
T
T
Same as I1, except write Flash at maximum rate,
CE_E=0, ADC_E=0.
I
A
A
MPU_DIV
≤ 25 °C
= 85 °C
© 2008–2011 Teridian Semiconductor Corporation
Table 95
=
0
4.3
I -
MPU_DIV
below include only the current consumed by the 71M6543.
=
3
71M6543G/GH
71M6543G/GH
71M6543G/GH
71M6543G/GH
71M6543G/GH
71M6543G/GH
71M6543G/GH
71M6543G/GH
71M6543G/GH
71M6543G/GH
71M6543F/H
71M6543F/H
71M6543F/H
71M6543F/H
71M6543F/H
71M6543F/H
71M6543F/H
71M6543F/H
71M6543F/G
71M6543F/G
71M6543
71M6543
71M6543
71M6543
71M6543
71M6543
71M6543
71M6543
71M6543
71M6543
Device
-300
-300
-300
Min
Typ
240
260
7.2
7.5
6.4
6.7
2.9
3.0
7.3
7.7
6.5
6.9
3.0
3.1
0.4
0.5
2.4
2.6
0.4
3.0
1.1
1.8
0.7
1.5
7.1
7.3
24
0
0
0
+300
Max
0.65
300
108
300
410
420
8.5
8.8
7.3
7.7
3.8
3.9
8.7
9.1
7.5
7.9
3.9
3.9
0.6
3.2
3.5
3.4
4.1
1.7
3.2
8.7
8.7
36
11
MHz
Unit
mA/
v1.2
mA
mA
mA
mA
mA
mA
mA
mA
mA
nA
nA
µA
µA
µA
nA
nA
nA
nA
µA
µA
µA