71M6543F Maxim, 71M6543F Datasheet - Page 73

• Manufacturer Part Number: 71M6543F
• Description: The 71M6543F/71M6543H are Teridian's 4th-generation polyphase metering system-on-chips (SoCs) with a 5MHz, 8051-compatible MPU core, low-power real-time clock (RTC) with digital temperature compensation, flash memory, and LCD driver
• Manufacturer: Maxim

2.5.14 Test Ports (TMUXOUT and TMUX2OUT Pins)
Two independent multiplexers allow the selection of internal analog and digital signals for the TMUXOUT
and TMUX2OUT pins. These pins are multiplexed with the SEG47 and SEG46 function. In order to function
as test pins, LCD_MAP[46] (I/O RAM 0x2406[6]) and LCD_MAP[47] (I/O RAM 0x2406[7]) must be 0.
One of the digital or analog signals listed in Table 61 can be selected to be output on the TMUXOUT pin.
The function of the multiplexer is controlled with the I/O RAM register TMUX[4:0] (I/O RAM 0x2502[4:0], as
shown in
One of the digital or analog signals listed in Table 61 can be selected to be output on the TMUX2OUT pin.
The function of the multiplexer is controlled with the I/O RAM register TMUX2[4:0] (I/O RAM 0x2503[4:0]), as
shown
The TMUXOUT and TMUX2OUT pins may be used for diagnosis purposes or in production test. The
RTC 1-second output may be used to calibrate the crystal oscillator. The RTC 4-second output provides
even higher precision.
v1.2
The TMUX and TMUX2 I/O RAM locations are non-volatile and their contents are preserved by
battery power and across resets.
in.
Note:
All
Table
TMUX[5:0]
TMUX[5:0]
1C
1D
1B
1F
A
D
E
1
9
60.
values which are not shown are reserved.
Signal Name
RTCLK
WD_RST
CKMPU
V3AOK bit
V3OK bit
MUX_SYNC
CE_BUSY interrupt
CE_XFER interrupt
RTM output from CE
© 2008–2011 Teridian Semiconductor Corporation
Table 60: TMUX[4:0] Selections
Description
32.768 kHz clock waveform
Indicates when the MPU has reset the watchdog timer. Can be
monitored to determine spare time in the watchdog timer.
MPU clock – see
Indicates that the V3P3A pin voltage is ≥ 3.0 V. The V3P3A and
V3P3SYS pins are expected to be tied together at the PCB level.
The 71M6543 monitors the V3P3A pin voltage only.
Indicates that the V3P3A pin voltage is ≥ 2.8 V. The V3P3A and
V3P3SYS pins are expected to be tied together at the PCB level.
The 71M654 monitors the V3P3A pin voltage only.
Internal multiplexer frame SYNC signal. See
Figure
See
See
2.3.3
2.3.5
5.
on page
on page
Table 8
71M6543F/H and 71M6543G/GH Data Sheet
25
26
and
Figure 12
on page
Figure 4
46
and
73